Datasheet
2010 Microchip Technology Inc. DS39969B-page 31
PIC24FJ256DA210 FAMILY
TCK 27 38 J6 I ST JTAG Test Clock Input.
TDI 28 60 G11 I ST JTAG Test Data Input.
TDO 24 61 G9 O — JTAG Test Data Output.
TMS 23 17 G3 I ST JTAG Test Mode Select Input.
USBID 33 51 K10 I ST USB OTG ID (OTG mode only).
USBOEN 12 21 H2 O — USB Output Enable Control (for external transceiver).
V
BUS 34 54 H8 I ANA USB Voltage, Host mode (5V).
V
BUSCHG 49 76 A11 O — External USB VBUS Charge Output.
V
BUSON 11 20 H1 O — USB OTG External Charge Pump Control.
V
BUSST 58 87 B6 I ANA USB OTG Internal Charge Pump Feedback Control.
V
BUSVLD 58 87 B6 I ST USB VBUS Boost Generator, Comparator Input 1.
V
CAP 56 85 B7 P — External Filter Capacitor Connection (regulator enabled).
V
CMPST1 58 87 B6 I ST USB VBUS Boost Generator, Comparator Input 1.
V
CMPST2 59 88 A6 I ST USB VBUS Boost Generator, Comparator Input 2.
V
CPCON 49 76 A11 O — USB OTG VBUS PWM/Charge Output.
V
DD 10, 26, 38 2, 16, 37,
46, 62
C2, C9, F8,
G5, H6, K8,
H4, E5
P — Positive Supply for Peripheral Digital Logic and I/O Pins.
VMIO 14 23 J2 I ST USB Differential Minus Input/Output (external transceiver).
VPIO 13 22 J1 I ST USB Differential Plus Input/Output (external transceiver).
V
REF-1528, 24
(4)
L2, K1
(4)
I ANA A/D and Comparator Reference Voltage (low) Input.
V
REF+1629, 25
(4)
K3, K2
(4)
I ANA A/D and Comparator Reference Voltage (high) Input.
V
SS 9, 25, 41 15, 36, 45,
65, 75
B10, F5,
F10, G6,
G7, H3, D4,
D5
P — Ground Reference for Logic and I/O Pins.
V
SYNC 1 96 C3 O — Graphics Display Vertical Sync Pulse.
V
USB 35 55 H9 P — USB Voltage (3.3V).
TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O
Input
Buffer
Description
64-Pin
TQFP/QFN
100-Pin
TQFP
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
2
C™ = I
2
C/SMBus input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
(CW3<12>) bit is programmed to ‘0’.
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.