Datasheet

PIC24FJ256DA210 FAMILY

DS39969B-page 276  2010 Microchip Technology Inc.

R-0, HSC U-0 R/C-0, HS R/C-0, HS R-0, HSC R-1, HSC R/W-0 R/W-0

BUSY

—

ERROR TIMEOUT AMREQ CURMST MSTSEL1 MSTSEL0

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RADDR23 RADDR22 RADDR21 RADDR20 RADDR19 RADDR18 RADDR17 RADDR16

bit 7 bit 0

Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 BUSY: Busy bit (Master mode only)

1 = Port is busy

0 = Port is not busy

bit 14 Unimplemented: Read as ‘0’

bit 13 ERROR: Error bit

1 = Transaction error (illegal transaction was requested)

0 = Transaction completed successfully

bit 12 TIMEOUT: Time-Out bit

1 = Transaction timed out

0 = Transaction completed successfully

bit 11 AMREQ: Alternate Master Request bit

1 = The Alternate Master is requesting use of EPMP

0 = The Alternate Master is not requesting use of EPMP

bit 10 CURMST: Current Master bit

1 = EPMP access is granted to CPU

0 = EPMP access is granted to alternate master

bit 9-8 MSTSEL<1:0>: Parallel Port Master Select bits

11 = Alternate master I/Os direct access (EPMP Bypass mode)

10 = Reserved

01 = Alternate master

00 = CPU

bit 7-0 RADDR<23:16>: Parallel Master Port Reserved Address Space bits

(1)

Note 1: If RADDR<23:16> = 00000000, then the last EDS address for Chip Select 2 will be 0xFFFFFF.