Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 226  2010 Microchip Technology Inc.
REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
I2CEN
— I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module. All I
2
C™ pins are controlled by port functions
bit 14 Unimplemented: Read as ‘0’
bit 13 I2CSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I
2
C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN =
1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of slave transmission. Hardware is clear at the end of slave reception.
If STREN =
0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11 IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit
1 = IPMI Support mode is enabled; all addresses are Acknowledged
0 = IPMI mode is disabled
bit 10 A10M: 10-Bit Slave Addressing bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specifications
0 = Disables the SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I
2
C slave)
1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)
0 = General call address disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I
2
C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receive clock stretching
0 = Disables software or receive clock stretching