Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 20  2010 Microchip Technology Inc.
FIGURE 1-1: PIC24FJ256DA210 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
EDS and Table
Data Access
Control Block
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Extended Data
Data Latch
16
Address Bus
Literal Data
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
LVD & BOR
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
VCAP
ENVREG
PORTA
(1)
PORTC
(1)
(12 I/O)
(8 I/O)
PORTB
(16 I/O)
Note 1:
Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count .
2: These peripheral I/Os are only accessible through remappable pins.
3: Not available on 64-pin devices (PIC24FJxxxDAx06).
PORTD
(1)
(16 I/O)
Comparators
(2)
Timer2/3
(2)
Timer1
RTCC
IC
ADC
10-Bit
OC/PWM SPI
I
2
C
Timer4/5
(2)
™
EPMP/PSP
(3)
1-9
(2)
ICNs
(1)
UART
REFO
PORTE
(1)
PORTG
(1)
(10 I/O)
(12 I/O)
PORTF
(1)
(10 I/O)
1/2/3
(2)
1/2/3
1/2/3/4
(2)
1-9
(2)
CTMU
(2)
USB OTG
Graphics
Controller
Up to 0x7FFF
Space
Program Memory/