Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 10  2010 Microchip Technology Inc.
Pin Diagram – Top View (121-Pin BGA)
(1)
135
10 11
A
RE4 RE3
HSYNC/
RE0 RG0 RF1
ENVREG
N/C RD12 GD11/
GD7/
RD1
B
N/C GCLK/ RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14
C
RE6
VDD
VSYNC/
RG14
GEN/
N/C
RD7
RD4
VDD
RC13 RD11
D
GD0/
RE7
RE5
VSS VSS
N/C
RD6
RD13
RD0 n/c
RD10
E
RC4
GD1/
RG6
GD8/
VDD RG1
N/C
RA15 RD8
GD10/
RA14
F
MCLR
RG8 RG9 RG7
VSS
n/c N/C
VDD
OSCI/
VSS
OSCO/
G
RE8 RE9 RA0
N/C
VDD VSS VSS N/C RA5
RA3
RA4
H
PGEC3/ PGED3/
VSS VDD
N/C VDD n/c
VBUS/
VUSB
D+/RG2 RA2
J
GD5/ GD6/
PGED2/
AVDD
RB11 RA1 RB12
N/C
N/C
GD9/RF8 D-/RG3
K
PGEC1/ PGED1/
RA10
GD12/
N/C
RF12 RB14
VDD
GD15/ USBID/ GD3/
L
PGEC2/ RA9
AVSS
GD13/ RB10 GD2/ RB13
RB15
GD14/ RF4 RF5
24 6
Note 1: See Table 3 for complete functional pinout descriptions.
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
Shaded pins indicate pins tolerant to up to +5.5V.
RF7
RG13
RD2
RG15
RG12 RA6
RC1
RC3
RC2
RD9
RC12 RC15
RB3 RB2
RB8
RD15
RF3 RF2
RB9
RF13 RD14
RB5
GD4/RB4
RB1 RB0
RB6
RB7
GPWR
9
8
7