Datasheet

© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 85
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
— —INT2IET5IE
(1)
T4IE
(1)
— — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT1IE CNIE CMPIE MI2C1IE SI2C1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12 T5IE: Timer5 Interrupt Enable bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11 T4IE: Timer4 Interrupt Enable bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 T5IE: Timer5 Interrupt Enable bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4 INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 3 CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 2 CMPIE: Comparator Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Note 1: This bit is available in PIC24FJ32MC101/102/104 devices only.