Datasheet

© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 53
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
TABLE 4-31: SYSTEM CONTROL REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
RCON 0740 TRAPR IOPUWR CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR
xxxx
(1)
OSCCON 0742 COSC<2:0> NOSC<2:0> CLKLOCK IOLOCK LOCK —CF LPOSCEN OSWEN 0300
(2)
CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> 3040
OSCTUN 0748
TUN<5:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values dependent on type of Reset.
2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 4-32: NVM REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
NVMCON 0760 WR WREN WRERR ERASE —NVMOP<3:0>
0000
(1)
NVMKEY 0766
NVMKEY<7:0>
0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-33: PMD REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
PMD1 0770 T5MD
(1)
T4MD
(1)
T3MD T2MD T1MD
PWM1MD
I2C1MD
U1MD
SPI1MD
AD1MD 0000
PMD2 0772
IC3MD IC2MD IC1MD —OC2MDOC1MD0000
PMD3 0774
CMPMD RTCCMD 0000
PMD4 0776
—CTMUMD 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is available in PIC24FJ32MC101/102/104 devices only.