Datasheet

© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 31
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
4.0 MEMORY ORGANIZATION
The PIC24FJ16MC101/102 and PIC24FJ32MC101/
102/104 architecture features separate program and
data memory spaces and buses. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1 Program Address Space
The program address memory space of the
PIC24FJ16MC101/102 and PIC24FJ32MC101/102/
104 devices is 4M instructions. The space is
addressable by a 24-bit value derived either from the
23-bit Program Counter (PC) during program execution,
or from table operation or data space remapping as
described in Section 4.4 “Interfacing Program and
Data Memory Spaces”.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The program memory maps for the PIC24FJ16MC101/
102 and PIC24FJ32MC101/102/104 family of devices
are shown in Figure 4-1 and Figure 4-2.
FIGURE 4-1: PROGRAM MEMORY MAP FOR PIC24FJ16MC101/102 DEVICES
Note 1: This data sheet summarizes the features
of the PIC24FJ16MC101/102 and
PIC24FJ32MC101/102/104 family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 3. “Data Memory”
(DS39717) and Section 4. “Program
Memory” (DS39715) in the “PIC24F
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
2: It is important to note that the
specifications in Section 26.0 “Electri-
cal Characteristics” of this data sheet,
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
Reset Address
0x000000
0x0000FE
0x000002
0x000100
Device Configuration
User Program
Flash Memory
0x002BFC
0x002BFA
(5.6K instructions)
0x800000
0xF80000
Shadow Registers
0xF80017
0xF80018
DEVID (2)
0xFEFFFE
0xFF0000
0xFFFFFE
0xF7FFFE
Unimplemented
(Read ‘0’s)
GOTO Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
0x000104
Alternate Vector Table
Reserved
Interrupt Vector Table
Configuration Memory Space
User Memory Space
Flash Configuration
Words
(1)
0x002C00
0x002BFE
Note 1: On reset, these bits are automatically copied into the device Configuration shadow registers.