Datasheet

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
DS39997C-page 26 Preliminary © 2011-2012 Microchip Technology Inc.
FIGURE 3-1: PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 CPU CORE BLOCK
DIAGRAM
Instruction
Decode and
Control
PCH PCL
Program Counter
16-bit ALU
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
EA MUX
Interrupt
Controller
Stack
Control
Logic
Loop
Control
Logic
Control Signals
to Various Blocks
Literal Data
16
16
16
To Peripheral Modules
Data Latch
Address
Latch
16
X RAM
Address Generator Units
X Data Bus
17 x 17
Divide Support
16
16
23
23
16
8
PSV and Table
Data Access
Control Block
16
16
16
Program Memory
Data Latch
Address Latch
Multiplier