Datasheet

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 DS39997C-page 236 Preliminary © 2011-2012 Microchip Technology Inc.
The Configuration Shadow register map is shown in Table 23-1.
TABLE 23-1: CONFIGURATION SHADOW REGISTER MAP
The Configuration Flash Words map is shown in Table 23-2.
TABLE 23-2: CONFIGURATION FLASH WORDS FOR PIC24FJ16MC10X DEVICES
TABLE 23-3: CONFIGURATION FLASH WORDS FOR PIC24FJ32MC10X DEVICES
File Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FGS F80004
— — — — — —GCPGWRP
FOSCSEL F80006 IESO PWMLOCK
— WDTWIN<1:0> FNOSC<2:0>
FOSC F80008 FCKSM<1:0> IOL1WAY
— — OSCIOFNC POSCMD<1:0>
FWDT F8000A FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
FPOR F8000C PWMPIN HPOL LPOL ALTI2C1
— — — —
FICD F8000E Reserved
(1)
— Reserved
(2)
Reserved
(2)
— —ICS<1:0>
Legend: — = unimplemented, read as ‘1’.
Note 1: This bit is reserved for use by development tools and must be programmed as ‘1’.
2: This bit is reserved; program as ‘0’.
File
Name
Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2 002BFC
—IESOPWMLOCK
(2)
PWMPIN
(2)
WDTWIN<1:0> FNOSC<2:0> FCKSM<1:0> OSCIOFNC IOL1WAY LPOL
(2)
ALTI2C1 POSCMD<1:0>
CONFIG1 002BFE
— Reserved
(3)
Reserved
(3)
GCP GWRP Reserved
(4)
HPOL
(2)
ICS<1:0> FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
Legend: — = unimplemented, read as ‘1’.
Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
2: This bit is reserved on PIC24FJ16MC10X devices and reads as ‘1’.
3: This bit is reserved; program as ‘0’.
4: This bit is reserved for use by development tools and must be programmed as ‘1’.
File
Name
Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2 0057FC
—IESOPWMLOCK
(2)
PWMPIN
(2)
WDTWIN<1:0> FNOSC<2:0> FCKSM<1:0> OSCIOFNC IOL1WAY LPOL
(2)
ALTI2C1 POSCMD<1:0>
CONFIG1 0057FE
— Reserved
(3)
Reserved
(3)
GCP GWRP Reserved
(4)
HPOL
(2)
ICS<1:0> FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
Legend: — = unimplemented, read as ‘1’.
Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
2: This bit is reserved on PIC24FJ32MC10X devices and reads as ‘1’.
3: This bit is reserved; program as ‘0’.
4: This bit is reserved for use by development tools and must be programmed as ‘1’.