Datasheet

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
DS39997C-page 216 Preliminary © 2011-2012 Microchip Technology Inc.
REGISTER 20-5: CMxFLTR: COMPARATOR FILTER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 I-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CFSEL<2:0> CFLTREN CFDIV<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = Reserved
110 = Reserved
101 = Timer3
100 = Timer2
011 = Reserved
010 = PWM Special Event Trigger
001 = F
OSC
000 = FCY
bit 3 CFLTREN: Comparator Filter Enable bit
1 = Digital filter enabled
0 = Digital filter disabled
bit 2-0 CFDIV<2:0>: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1