PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM) Operating Conditions Advanced Analog Features • 3.0V to 3.6V, -40ºC to +125ºC, DC to 16 MIPS • ADC module: - 10-bit, 1.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed in Table 1 and table. The following pages show their pinout diagrams.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Pin Diagrams = Pins are up to 5V tolerant 20-Pin PDIP/SOIC/SSOP MCLR PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 PGEC3/SOSCO/AN10/T1CK/CN0/RA4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PIC24FJ32MC101 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4(1
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Pin Diagrams (Continued) = Pins are up to 5V tolerant 28-Pin SPDIP/SOIC/SSOP MCLR PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 PGEC3/SOSCO/AN10/T1CK/CN0/RA4 VDD FLTB1(2)/ASDA1/RP5(1)/CN27/RB5 1 2 3 4 5 6 7 8 9
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Pin Diagrams (Continued) 28-Pin QFN(2) PWM1L1/RP15(1)/CN11/RB15 PWM1H1/RTCC/RP14(1)/CN12/RB14 AVSS MCLR AVDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 = Pins are up to 5V tolerant 28 27 26 25 24 23 22 PGED1/AN2/C2INA/C1INC/CTCMP/RP0(1)/CN4/RB0 1 21 PWM1L2/RP13(1)/CN13/RB13 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1 2 20 PWM1H2/RP12(1)/CN14/RB12 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 19 PWM1L3/RP11(1)/CN15/RB11
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Pin Diagrams (Continued) 28-Pin QFN(2) PWM1H1/RTCC/RP14(1)/CN12/RB14 PWM1L1/RP15(1)/CN11/RB15 AVSS MCLR AVDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 = Pins are up to 5V tolerant 28 27 26 25 24 23 22 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 21 PWM1L2/RP13(1)/CN13/RB13 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1 2 20 PWM1H2/RP12(1)/CN14/RB12 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 19 PWM1L3/RP11(1)/CN15/RB11 18 P
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Pin Diagrams (Continued) 36-Pin VTLA MCLR AVDD AVSS PWM1L1/RP15(1)/CN11/RB15 PWM1H1/RTCC/RP14(1)/CN12/RB14 35 N/C PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 36 N/C PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 = Pins are up to 5V tolerant 34 33 32 31 30 29 28 27 PWM1L2/RP13(1)/CN13/RB13 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 26 PWM1H2/RP12(1)/CN14/RB12 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 2 25 PWM1L3/RP11(1)/CN15/RB11 (1) 3 24 PW
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Pin Diagrams (Continued) 36-Pin VTLA(2) PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 PWM1H1/RTCC/RP14(1)/CN12/RB14 33 PWM1L1/RP15(1)/CN11/RB15 N/C 34 AVSS N/C 35 MCLR PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 36 AVDD PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 = Pins are up to 5V tolerant 32 31 30 29 28 27 PWM1L2/RP13(1)/CN13/RB13 1 26 PWM1H2/RP12(1)/CN14/RB12 (1) 2 25 PWM1L3/RP11(1)/CN15/RB11 (1) AN4/C3INC/C2INC/RP2 /CN6/RB2 3 24 PWM1H3/RP10(1)/CN16
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Pin Diagrams (Continued) 44-Pin TQFP PGEC3/SOSCO/AN10/T1CK/CN0/RA4 RA9 AN11/RP19(1)/CN28/RC3 AN12/RP20(1)/CN25/RC4 AN15/RP21(1)/CN26/RC5 VSS VDD FLTB1(2)/ASDA1/RP5(1)/CN27/RB5 FLTA1(2)/ASCL1/RP6(1)/CN24/RB6 INT0/RP7(1)/CN23/RB7 SCL1/RP8(1)/CN22/RB8 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 SDA1/RP9(1)/CN21/RB9 1 33 PEGED3/SOSCI/AN9/RP4(1)/CN1/RB4 RP22(1)/CN18/RC6 2 32 RA8 RP23(1)/CN17/RC7 3 31 OSC2/CLK0/CN29/RA3 RP24(1
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Pin Diagrams (Continued) 44-pin QFN(2) PGEC3/SOSCO/AN10/T1CK/CN0/RA4 RA9 AN11/RP19(1)/CN28/RC3 AN12/RP20(1)/CN25/RC4 AN15/RP21(1)/CN26/RC5 VSS VDD FLTB1(3)/ASDA1/RP5(1)/CN27/RB5 FLTA1(3)/ASCL1/RP6(1)/CN24/RB6 INT0/RP7(1)/CN23/RB7 SCL1/RP8(1)/CN22/RB8 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 (1) SDA1/RP9 /CN21/RB9 1 33 (1) RP22 /CN18/RC6 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 2 32 RA8 RP23(1)/CN17/RC7 3 31 OSC2/CLKO/CN29/RA3
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Pin Diagrams (Continued) 44-Pin TLA(2) PGEC3/SOSCO/AN10/T1CK/CN0/RA4 AN11/RP19(1)/CN28/RC3 AN12/RP20(1)/CN25/RC4 AN15/RP21(1)/CN26/RC5 1 32 RA8 RP22(1)/CN18/RC6 2 31 OSC2/CLKO/CN29/RA3 RP23(1)/CN17/RC7 3 30 OSC1/CLKI/CN30/RA2 RP24(1)/CN20/RC8 4 29 VSS RP25(1)/CN19/RC9 5 28 VDD VSS 6 27 AN8/RP18(1)/CN10/RC2 RA9 43 42 41 40 39 38 37 36 35 34 33 VSS 44 SDA1/RP9(1)/CN21/RB9 VDD INT0/RP7(1)/CN23/RB7 FLTB1(3)/ASDA1/RP5(1)/CN27/RB5 SCL
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Table of Contents PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 Product Families ........................................................................................... 2 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ...................................
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PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Referenced Sources This device data sheet is based on the following individual chapters of the “PIC24F Family Reference Manual”. These documents should be considered as the primary reference for the operation of a particular module or device feature. Note: To access the documents listed below, browse to the documentation section of the PIC24FJ16MC102 product page of the Microchip Web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest family reference sections of the “PIC24F Family Reference Manual”, which are available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 1-1: PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 BLOCK DIAGRAM PSV and Table Data Access Control Block X Data Bus Interrupt Controller PORTA 16 8 16 16 Data Latch 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 X RAM PORTB Address Latch 16 23 16 Remappable Pins Address Generator Units Address Latch Program Memory EA MUX Data Latch ROM Latch 24 Instruction Reg Control Signals to Various Blocks Timing Generati
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type PPS AN0-AN10(5) AN11, AN12, AN15(4) I Analog No Analog input channels. CLKI CLKO I O ST/CMOS — No No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS SCK1 SDI1 SDO1 SS1 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. SCL1 SDA1 ASCL1 ASDA1 I/O I/O I/O I/O ST ST ST ST No No No No Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 I/O I I/O I I/O I ST ST ST ST ST ST No No No No No No Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 20 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.2 The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD, and AVSS is required. Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24F Family Reference Manual”.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 10 µF Tantalum R R1 VSS VDD 2.4 VCAP VDD PIC24F VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(1) 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1Ω and the inductor capacity greater than 10 mA.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 2.5 ICSP Pins 2.6 The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz (for MSPLL mode) or 3 MHz < FIN < 8 MHz (for ECPLL mode) to comply with device PLL start-up conditions. HSPLL mode is not supported.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 3.0 CPU Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS39703) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: It is important to note that the specifications in Section 26.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 3-1: PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block X Data Bus Interrupt Controller 8 16 16 16 Data Latch 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 X RAM Address Latch 23 16 Address Generator Units Address Latch Program Memory EA MUX Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction Reg Literal Data Instruction Decode and C
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 3-2: PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 — bit 15 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — R/C-0 IPL3(1) R/W-0 PSV U-0 — U-0 — bit 7 bit 0 Legend: R = Readable bit 0’ = Bit is cleared bit 15-4 bit 3 bit 2 bit 1-0 Note 1: C = Clear only bit W = Writable bit ‘x = Bit is unknown -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented: Read as ‘0’ IPL3: CPU Interrupt Priority
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 3.4 Arithmetic Logic Unit (ALU) 3.4.2 The PIC24FJ16MC101/102 and PIC24FJ32MC101/ 102/104 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts, and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV), and Digit Carry (DC) Status bits in the SR register.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 4.0 MEMORY ORGANIZATION 4.1 Program Address Space The program address memory space of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/ 104 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.4 “Interfacing Program and Data Memory Spaces”.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 4-2: PROGRAM MEMORY MAP FOR PIC24FJ32MC101/102/104 DEVICES GOTO Instruction Reset Address User Memory Space Interrupt Vector Table Reserved Alternate Vector Table User Program Flash Memory (11.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All PIC24FJ16MC101/102 and PIC24FJ32MC101/102/ 104 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 4.2 Data Address Space The PIC24FJ16MC101/102 and PIC24FJ32MC101/ 102/104 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-4. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 4-4: DATA MEMORY MAP FOR PIC24FJ16MC101/102 DEVICES WITH 1 KB RAM MSB Address MSb 2 Kbyte SFR Space LSb 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 1 Kbyte SRAM Space LSB Address 16 bits 0x0BFF 0x0C01 0x0BFE 0x0C00 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFE 0xFFFF © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 4-5: DATA MEMORY MAP FOR PIC24FJ32MC101/102/104 DEVICES WITH 2 KB RAM MSB Address MSb 2 Kbyte SFR Space LSb 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 0x0FFF 0x1001 0x0FFE 0x1000 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFE 0xFFFF DS39997C-page 36 8 Kbyte Near Data Space X Data RAM (X) 2 Kbyte SRAM Space LSB Address 16 bits Preliminary © 2011-2012 Microchi
SFR Name CPU CORE REGISTERS MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Preliminary WREG0 0000 Working Register 0 xxxx WREG1 0002 Working Register 1 xxxx WREG2 0004 Working Register 2 xxxx WREG3 0006 Working Register 3 xxxx WREG4 0008 Working Register 4 xxxx WREG5 000A Working Register 5 xxxx WREG6 000C Working Register 6 xxxx WREG7 000E Working Register 7 xxxx WREG8 0010 W
CHANGE NOTIFICATION REGISTER MAP FOR PIC24FJXXMC101 DEVICES SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CNEN1 0060 — CN14IE CN13IE CN12IE CN11IE — — — — — CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CNEN2 0062 — CN29IE — — — — — CN23IE CN22IE CN21IE — — — — — 0000 CNPU1 0068 — — — — — — CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 CNPU2 006A — — —
SFR Name INTERRUPT CONTROLLER REGISTER MAP SFR Addr Bit 15 INTCON1 0080 INTCON2 0082 IFS0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — 0000 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 NSTDIS — — — — — — — — — — ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 MATHERR ADDRERR STKERR OSCFAIL IFS1 0086 — — IN
SFR Name SFR Addr TIMERS REGISTER MAP FOR PIC24FJ16MC101/102 DEVICES Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TMR2 0106 TON — TSIDL — — — TMR3HLD 0108 — — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 FFFF TGATE TCKPS<1:0> — TSYNC TCS — 0000 Timer2 Register 0000 Timer3 Holding Register (for 32-bit timer operations only) xxxx TMR3 010A Timer3 Register 0000 PR2
INPUT CAPTURE REGISTER MAP SFR Name SFR Addr IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 IC3BUF 0148 IC3CON 014A Legend: Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — Bit 8 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> Bit 0 Input 1 Capture Register — 0000 Input 2 Capture Register — — ICSIDL — — — — — xxxx ICTMR 0000 Input 3 Capture Register — — ICSID
SFR Name Addr.
SFR Name SFR Addr UART1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR Bit 2 Bit 1 All Resets STSEL 0000 URXDA 0110 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT U1TXREG 0224 — — — — — — — UART Transmit Register xxxx U1RXREG 0226 — — — — — — — UART Receive Register 0000 U1BRG
ADC1 REGISTER MAP FOR PIC24FJXXMC101 DEVICES Preliminary Addr ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC Data Buffer 1 xxxx ADC1BUF2 0304 ADC Data Buffer 2 xxxx ADC1BUF3 0306 ADC Data Buffer 3 xxxx ADC1BUF4 0308 ADC Data Buffer 4 xxxx ADC1BUF5 030A ADC Data Buffer 5 xxxx ADC1BUF6 030C ADC Data Buffer 6 xxxx ADC1BUF7 030E ADC Data Buffer 7 xxxx ADC1BUF8 0310 ADC Data Buffer 8 xxxx ADC1BUF9 0312 ADC Data Buffer 9 xxxx ADC1BUFA 0314 ADC Data Buffer 10 x
File Name Addr ADC1 REGISTER MAP FOR PIC24FJXXMC102 DEVICES Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Preliminary ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC Data Buffer 1 xxxx ADC1BUF2 0304 ADC Data Buffer 2 xxxx ADC1BUF3 0306 ADC Data Buffer 3 xxxx ADC1BUF4 0308 ADC Data Buffer 4 xxxx ADC1BUF5 030A ADC Data Buffer 5 xxxx ADC1BUF6 030C ADC Data Buffer 6 xxxx ADC1BUF7 030E ADC
ADC1 REGISTER MAP FOR PIC24FJ32104 DEVICES Bit 15 Preliminary Addr ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC Data Buffer 1 xxxx ADC1BUF2 0304 ADC Data Buffer 2 xxxx ADC1BUF3 0306 ADC Data Buffer 3 xxxx ADC1BUF4 0308 ADC Data Buffer 4 xxxx ADC1BUF5 030A ADC Data Buffer 5 xxxx ADC1BUF6 030C ADC Data Buffer 6 xxxx ADC1BUF7 030E ADC Data Buffer 7 xxxx ADC1BUF8 0310 ADC Data Buffer 8 xxxx ADC1BUF9 0312 ADC Data Buffer 9 xxxx ADC1BUFA 0314 ADC Data Buffer
File Name Addr CTMUCON1 033A CTMUCON2 033C CTMUICON Legend: Addr ALRMVAL 0620 ALCFGRPT 0622 RTCVAL 0624 RCFGCAL 0626 Preliminary Legend: Bit 13 Bit 12 CTMUEN — CTMUSIDL TGEN EDG1MOD EDG1POL Bit 11 Bit 10 EDGEN EDGSEQEN EDG1SEL<3:0> Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 IDISSEN CTTRIG — — — EDG2STAT EDG1STAT EDG2MOD EDG2POL ITRIM<5:0> — IRNG<1:0> — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — — 0000 — — 0000 — — 0000 EDG2SEL<3:0> — — — — REAL-TIME CLO
File Name COMPARATOR REGISTER MAP Addr.
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24FJXXMC101 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 RPOR0 06C0 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — — RPOR6 06CC — — RPOR7 Legend: Bit 7 Bit 6 Bit 5 — — — RP0R<4:0> — — — RP4R<4:0> RP7R<4:0> — — — — RP9R<4:0> — — — RP8R<4:0> 0000 — RP13R<4:0> — — — RP12R<4:0> 0000 — — — RP15R<4:0> — 06CE x = unknown value on Reset, — = unimplemented, read as ‘0’.
File Name PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24FJ32MC104 DEVICES Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 RPOR1 06C2 — — — RP3R<4:0> — — — RP2R<4:0> 0000 RPOR2 06C4 — — — RP5R<4:0> — — — RP4R<4:0> 0000 RPOR3 06C6 — — — RP7R<4:0> — — — RP6R<4:0> 0000 RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000
File Name PORTA REGISTER MAP FOR PIC24FJXXMC101/102 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx ODCA 02C6 — — — — — — — — — — — — ODCA3 ODCA2 — —
File Name PORTB REGISTER MAP FOR PIC24FJ32MC104 DEVICES Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10
File Name SYSTEM CONTROL REGISTER MAP Addr Bit 15 Bit 14 RCON 0740 TRAPR IOPUWR OSCCON 0742 — Bit 13 Bit 12 — — COSC<2:0> Bit 11 Bit 10 — — — Bit 8 CM VREGS NOSC<2:0> Bit 5 Bit 4 Bit 3 Bit 2 EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) LOCK — CF — LPOSCEN OSWEN 0300(2) — — — — — — CLKDIV 0744 ROI 0748 — Legend: Note 1: 2: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 4.2.5 SOFTWARE STACK 4.2.6 In addition to its use as a working register, the W15 register in the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 4-34: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the MSb of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL and TBLRDH).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 5.0 FLASH PROGRAM MEMORY ICSP allows a device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows users to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 5.2 RTSP Operation 5.3.1 The PIC24FJ16MC101/102 and PIC24FJ32MC101/ 102/104 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions); and to program one word. Table 26-12 shows typical erase and programming times. The 8-row erase pages are edgealigned from the beginning of program memory, on boundaries of 1536 bytes. 5.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 R/W-0(1) U-0 — U-0 ERASE — R/W-0(1) U-0 R/W-0(1) R/W-0(1) R/W-0(1) (2) — NVMOP<3:0> bit 7 bit 0 Legend: SO = Satiable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Wri
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: SO = Satiable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS39997C-
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Reset” (DS39712) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: It is important to note that the specifications in Section 26.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 TRAPR bit 15 R/W-0 IOPUWR U-0 — U-0 — U-0 — U-0 — R/W-0 CM R/W-0 VREGS bit 8 R/W-0 EXTR bit 7 R/W-0 SWR R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1 BOR R/W-1 POR bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 6.1 System Reset • Cold Reset • Warm Reset A warm Reset is the result of all other Reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection bits (COSC<2:0>) in the Oscillator Control register (OSCCON<14:12>). A cold Reset is the result of a POR or a BOR.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 6-2: SYSTEM RESET TIMING VBOR Vbor VPOR VDD TPOR 1 POR TBOR 2 BOR 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Reset Device Status Run Time 1. 2. 3. 4. 5. 6. POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay TPOR has elapsed.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 6.2 POR 6.3 A POR circuit ensures the device is reset from poweron. The POR circuit is active until VDD crosses the VPOR threshold and the delay TPOR has elapsed. The delay TPOR ensures the internal device bias circuits become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 26.0 “Electrical Characteristics” for details.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 6.4 External Reset (EXTR) 6.6 The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 26.0 “Electrical Characteristics” for minimum pulse width specifications. The External Reset (MCLR) Pin (EXTR) bit in the Reset Control register (RCON) is set to indicate the MCLR Reset. 6.4.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 6.9 Illegal Condition Device Reset 6.9.3 If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a protected segment (Boot and Secure Segment), that operation will cause a security Reset.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 70 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupts” (DS39707) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Decreasing Natural Order Priority FIGURE 7-1: Note 1: DS39997C-page 72 PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interru
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 7-1: INTERRUPT VECTORS Vector Number Interrupt Request (IRQ) Number IVT Address AIVT Address 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00002C 0x00002E 0x000030 0x000032 0x000034 0x000036 0x000038 0x000114 0x000116 0x000118 0x00011A 0x00011C 0x00011E 0x000120 0x000122 0x000124 0x00
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 7-2: TRAP VECTORS Vector Number 7.3 IVT Address AIVT Address 0 0x000004 0x000104 Reserved 1 0x000006 0x000106 Oscillator Failure 2 0x000008 0x000108 Address Error 3 0x00000A 0x00010A Stack Error 4 0x00000C 0x00010C Math Error 5 0x00000E 0x00010E Reserved 6 0x000010 0x000110 Reserved 7 0x000012 0x000112 Reserved Interrupt Control and Status Registers 7.3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-1: U-0 — bit 15 R/W-0(3) IPL2(2) bit 7 SR: CPU STATUS REGISTER(1) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DC bit 8 R/W-0(3) IPL1(2) R/W-0(3) IPL0(2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 Legend: C = Clear only bit S = Set only bit ‘1’ = Bit is set R = Readable bit W = Writable bit ‘0’ = Bit is cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR x = Bit is unknown IPL<2:0>: CPU Interrupt Priority Level Status bits(2
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disable
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — INT2IF T5IF(1) T4IF(1) — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF CMPIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: Ext
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — IC3IF — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Int
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — CTMUIF — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — U1EIF FLTB1IF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = I
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS39997C-page 84 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — INT2IE T5IE(1) T4IE(1) — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE CMPIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE:
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — IC3IE — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Inte
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — CTMUIE — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — U1EIE FLTB1IE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = In
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-15: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt P
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-16: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC2IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bi
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-17: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 — R/W-0 R/W-0 U1RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 AD1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interru
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-19: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 — R/W-0 R/W-0 CNIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 CMPIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notificat
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 INT2IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T5IP<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-23: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 R/W-0 IC3IP<2:0> U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: External Interrupt 3 Priority bits 111 =
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-25: U-0 IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 R/W-1 — R/W-0 R/W-0 FLTA1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 RTCCIP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Prio
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-26: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 U1EIP<2:0> R/W-0 U-0 — R/W-0 R/W-0 R/W-0 FLTB1IP<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Prior
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-27: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 CTMUIP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Int
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 7-28: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrup
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 7.4 Interrupt Setup Procedures 7.4.1 7.4.3 INITIALIZATION To configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits into the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 8.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 8.1 CPU Clocking System 8.1.1.5 The PIC24FJ16MC101/102 and PIC24FJ32MC101/ 102/104 devices provide seven system clock options: • • • • • • • Fast RC (FRC) Oscillator FRC Oscillator with 4x PLL Primary (MS, HS or EC) Oscillator Primary Oscillator with 4x PLL Secondary (LP) Oscillator Low-Power RC (LPRC) Oscillator FRC Oscillator with postscaler 8.1.1 8.1.1.1 Fast RC The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 8.1.3 PLL CONFIGURATION EQUATION 8-2: The primary oscillator and internal FRC oscillator can optionally use an on-chip 4x PLL to obtain higher speeds of operation. F OSC = 1--- ( 8000000 ⋅4 ) = 16 MIPS F CY = ------------2 2 For example, suppose a 8 MHz crystal is being used with the selected oscillator mode of MS with PLL. This provides a Fosc of 8 MHz * 4 = 32 MHz. The resultant device operating speed is 32/2 = 16 MIPS.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 OSCCON: OSCILLATOR CONTROL REGISTER(1) REGISTER 8-1: U-0 R-0 — R-0 R-0 COSC<2:0> U-0 R/W-y R/W-y R/W-y NOSC<2:0>(2) — bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: 2: Writes to this register require an unlock sequence. Refer to Section 6.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 8-2: R/W-0 CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-1 R/W-1 DOZE<2:0>(2,3) ROI R/W-0 R/W-0 DOZEN(1,2,3) R/W-0 R/W-0 FRCDIV<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear t
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center frequ
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 8.2 Clock Switching Operation 2. Applications are free to switch among any of the four clock sources (Primary, LP, FRC, and LPRC) under software control at any time. To limit the possible side effects of this flexibility, PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 devices have a safeguard lock built into the switch process. Note: 8.2.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 9.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer (WDT)” (DS39697) and Section 10. “Power-Saving Features” (DS39698) in the “PIC24F Family Reference Manual”, which are available from the Microchip web site (www.microchip.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions • The WDT is automatically cleared • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Peripheral Module Disable”). • If the WDT or FSCM is enabled, the LPRC also remains active.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 T5MD(1) bit 15 R/W-0 T4MD(1) R/W-0 I2C1MD bit 7 U-0 — bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 18 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-1 bit 0 Note 1: 2: R/W-0 T2MD R/W-0 T1MD U-0 — R/W-0 PWM1MD U-0 — bit 8 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 T3MD R/W-0 U1MD U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 SPI1MD U-0 — U-0 — R/W-0 AD1MD(2) bit
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IC3MD IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 IC3MD: Input Capture 3 Mod
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — CMPMD RTCCMD — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Comparator Module Disable bit 1 = Co
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 114 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 10.0 I/O PORTS Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 10.1.1 10.3 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT, and TRIS registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 10.4 Peripheral Pin Select 10.4.2.1 Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) TABLE 10-1: Function Name Register Configuration Bits INT1 RPINR0 INT1R<4:0> External Interrupt 2 INT2 RPINR1 INT2R<4:0> Timer2 External Clock T2CK RPINR3 T2CKR<4:0> Timer3 External Clock T3CK RPINR3 T3CKR<4:0> Timer4 External Clock T4CK RPINR4 T4CKR<4:0>(2) Timer5 External Clock T5CK RPINR4 T5CKR<4:0>(2) Input Capture 1 IC1 RPINR7 IC1R<4:0> Input Capture 2 IC2 RPINR7 IC2R<4:
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) Function RPnR<4:0> Output Name NULL C1OUT C2OUT U1TX 00000 00001 00010 00011 RPn tied to default port pin RPn tied to Comparator 1 Output RPn tied to Comparator 2 Output RPn tied to UART1 Transmit U1RTS 00100 RPn tied to UART1 Ready To Send SCK1 01000 RPn tied to SPI Clock(1) SDO1 00111 RPn tied to SPI Data Output(1) SS1 01001 RPn tied to SPI1 Slave Select Output OC1 10010 RPn tied to Output
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 10.5 1. 2. 4. In some cases, certain pins as defined in Table 26-10 under “Injection Current”, have internal protection diodes to VDD and VSS. The term “Injection Current” is also referred to as “Clamp Current”. On designated pins, with sufficient external current limiting precautions by the user, I/O pin input voltages are allowed to be greater or less than the data sheet absolute maximum ratings with nominal VDD with respect to the VSS and VDD supplies.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 10.7 Peripheral Pin Select Registers The PIC24FJ16MC101/102 and PIC24FJ32MC101/ 102/104 family of devices implement 21 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (13) • Output Remappable Peripheral Registers (8) Note: Input and Output Register values can only be changed if OSCCON = 0. See Section 10.4.3.1 “Control Register Lock Sequence” for a specific command sequence.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 INT2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INT2R<4:0>: Assign External Inte
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T3CKR<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T2CKR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR<4:0>: Assign Time
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T5CKR<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T4CKR<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T5CKR<4:0>: Assig
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC2R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to th
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-6: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC3R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R<4:0>: Assign Input Capture 3
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-7: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OCFAR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Capt
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-8: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR<4:0>: Assign
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-9: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SCK1R<5:0>(1) bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SDI1R<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1SR<5:0>: Assi
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-10: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SS1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Sel
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-11: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP1R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP0R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R<4:0>: Peripheral Outp
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-13: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP5R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP4R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP5R<4:0>: Peripheral O
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-15: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP9R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP8R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP9R<4:0>: Peripheral Outp
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-17: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP13R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP12R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP13R<4:0>: Peripheral O
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-19: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP17R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP16R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP17R<4:0>: Periph
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 10-21: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP21R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP20R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP21R<4:0>: Peri
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 \ REGISTER 10-23: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP25R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP24R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP25R<4:0>: P
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 138 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 11.0 TIMER1 Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> U-0 R/W-0 R/W-0 U-0 — TSYNC TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit(1) 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 12.0 TIMER2/3 FEATURE Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS39704) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TIMER2/3 AND TIMER4/5(3) (32-BIT) BLOCK DIAGRAM(1,4) FIGURE 12-1: TxCK 1x Gate Sync 01 TCY 00 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS TGATE Q 1 Set TxIF Q D CK 0 PRy PRx ADC Event Trigger(2) Equal Comparator MSb LSb TMRx Reset TMRy Sync 16 To CTMU Filter Read TMRx/TMRy Write TMRx/TMRy 16 16 TMRxHLD 16 Data Bus<15:0> Note 1: 2: 3: 4: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TIMER2 AND TIMER4(1) (16-BIT) BLOCK DIAGRAM FIGURE 12-2: TCKPS<1:0> 2 TON TxCK 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS TCY 1 Set TxIF 0 Reset Q D Q CK TGATE Sync TMRx Comparator To CTMU Filter Equal PRx Note 1: FIGURE 12-3: Timer4 is available in PIC24FJ32MC101/102/104 devices only.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 12-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> R/W-0 U-0 R/W-0 U-0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer2 On bit When T32 = 1: 1 = Starts 32-bit Timer2/3 0 = Stops 32-bit Timer2/3 Wh
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 12-2: T3CON CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(2) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE(2) R/W-0 R/W-0 TCKPS<1:0>(2) U-0 U-0 R/W-0 U-0 — — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer3 On bit(2) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 1
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 12-3: T4CON CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> R/W-0 U-0 R/W-0 U-0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer4 On bit When T32 = 1: 1 = Starts 32-bit Timer4/5 0 = Stops 32-bit Timer4/5 Wh
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 12-4: T5CON CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(2) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE(2) R/W-0 R/W-0 TCKPS<1:0>(2) U-0 U-0 R/W-0 U-0 — — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer5 On bit(2) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 1
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 148 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 13.0 INPUT CAPTURE Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Input Capture” (DS39701) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 13.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 14.0 OUTPUT COMPARE The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the compare register value.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 14.1 Output Compare Modes application must disable the associated timer when writing to the output compare control registers to avoid malfunctions. Configure the Output Compare modes by setting the appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare Control register (OCxCON<2:0>). Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 HC R/W-0 — — — OCFLT OCTSEL R/W-0 R/W-0 R/W-0 OCM<2:0> bit 7 bit 0 Legend: HC = Cleared in Hardware HS = Set in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 154 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 15.0 MOTOR CONTROL PWM MODULE 15.1 Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 47. “Motor Control PWM” (DS39735), in the “PIC24F Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 15-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1) PWM1CON1 PWM Enable and Mode SFRs PWM1CON2 P1DTCON1 Dead-Time Control SFRs P1DTCON2 P1FLTACON Fault A Pin Control SFRs P1FLTBCON Fault B Pin Control SFRs P1OVDCON PWM Manual Control SFR PWM Generator 3 16-bit Data Bus P1DC3 Buffer P1DC3 Comparator PWM Generator 2(1) P1TMR Channel 3 Dead-Time Generator and Override Logic PWM1H3 Channel 2 Dead-Time Generator and Override Logic PWM1H2 PWM1L3
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 15.2 PWM Faults The Motor Control PWM module incorporates up to two fault inputs, FLTA1 and FLTB1. These fault inputs are implemented with Class B safety features. These features ensure that the PWM outputs enter a safe state when either of the fault inputs is asserted. Refer to Section 47. “Motor Control PWM” (DS39735), in the “PIC24F Family Reference Manual” for more information on the PWM faults.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 EXAMPLE 15-1: ASSEMBLY CODE EXAMPLE FOR WRITE-PROTECTED REGISTER UNLOCK AND FAULT CLEARING SEQUENCE ; FLTA1 pin must be pulled high externally in order to clear and disable the fault ; Writing to P1FLTBCON register requires unlock sequence mov mov mov mov mov mov #0xabcd,w10 #0x4321,w11 #0x0000,w0 w10, PWM1KEY w11, PWM1KEY w0,P1FLTACON ; ; ; ; ; ; Load first unlock key to w10 register Load second unlock key to w11 register Load desired value of P1FLTACON re
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-1: PxTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 PTEN — PTSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTOPS<3:0> R/W-0 R/W-0 PTCKPS<1:0> R/W-0 PTMOD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN: PWM Time Base Timer Enable bit 1 = PWM
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-2: R-0 PxTMR: PWM TIMER COUNT VALUE REGISTER R/W-0 R/W-0 R/W-0 PTDIR R/W-0 R/W-0 R/W-0 R/W-0 PTMR<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only) 1 = PWM time base
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-4: R/W-0 PxSECMP: SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 SEVTDIR(1) R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<14:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit(1)
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1(1) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PMOD3 PMOD2 PMOD1 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — PEN3H(2) PEN2H(2) PEN1H(2) — PEN3L(2) PEN2L(2) PEN1L(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-6: PWMxCON2: PWM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 SEVOPS<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IUE OSYNC UDIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SEVOPS<3:0>: PWM Special Ev
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-7: R/W-0 PxDTCON1: DEAD-TIME CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 DTBPS<1:0> R/W-0 R/W-0 R/W-0 DTB<5:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTAPS<1:0> R/W-0 R/W-0 R/W-0 DTA<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Cl
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-8: PxDTCON2: DEAD-TIME CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 DTS3A: Dead-Time Select for PWM3
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-9: PxFLTACON: FAULT A CONTROL REGISTER(1,2,3,4,5) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 FLTAM — — — — FAEN3 FAEN2 FAEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimpleme
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-10: PxFLTBCON: FAULT B CONTROL REGISTER(1,2,3,4) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 FLTBM — — — — FBEN3 FBEN2 FBEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemente
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-11: PxOVDCON: OVERRIDE CONTROL REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Uni
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-12: PxDC1: PWM DUTY CYCLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PDC1<15:0>: PWM Duty Cycle 1 Value bits REGISTER 15-13: PxDC2: PWM DUTY CYCLE REGISTE
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 15-15: PWMxKEY: PWM KEY UNLOCK REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWMKEY<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PWMKEY<15:0>: PWM Key Unlock bits If the PWMLOCK Configuration bit is asserted
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 16.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. “Serial Peripheral Interface (SPI)” (DS39699) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 16.1 1. 5. Note: 16.2.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en554339 KEY RESOURCES • Section 23.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 16.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 SSEN(2) CKP MSTEN R/W-0 R/W-0 R/W-0 R/W-0 SPRE<2:0>(3) R/W-0 PPRE<1:0>(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented:
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: The CKE bit is not used in the Framed SPI modes.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 17.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS39702) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 17-1: I2C™ BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS39997C-page
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Set in hardware HC = Cleared in hardware -n = Value at POR ‘1’ = Bit
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared -n = Value at POR ‘1’ = Bit is s
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented:
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 184 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 18.1 1. 2. UART Helpful Tips 18.2 In multi-node direct-connect UART networks, UART receive inputs react to the complementary logic level defined by the URXINV bit (UxMODE<4>), which defines the idle state, the default of which is logic high, (i.e., URXINV = 0).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 18.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0> R/W-0 R-1 R-0 R-0 R/C-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 19.2 ADC Initialization To configure the ADC module: Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 46.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 19-1: ADC1 BLOCK DIAGRAM FOR PIC24FJXXMC101 DEVICES CTMUI(1) CTMU TEMP(1) Open(2) AN0-AN3 AN9(3) AN10(3) S&H0 Channel Scan CH0SA<4:0> CH0 + CH0SB<4:0> - CSCNA AN1 VREFL CH0NA CH0NB AN0 AVSS AVDD AN3 S&H1 + - CH123SA CH123SB CH1 AN9(3) VCFG<2:0> ADC1BUF0 VREFL ADC1BUF1 ADC1BUF2 VREFH VREFL CH123NA CH123NB SAR ADC AN1 S&H2 CH123SA CH123SB CH2 + ADC1BUFE - ADC1BUFF AN10(3) VREFL CH123NA CH123NB AN2 S&H3 + CH123SA CH123SB CH3 - VRE
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 19-2: ADC1 BLOCK DIAGRAM FOR PIC24FJXXMC102 DEVICES CTMU TEMP(1) Open(2) AN0-AN5 AN9(3) AN10(3) CTMUI(1) S&H0 Channel Scan + CH0SA<4:0> CH0 CH0SB<4:0> - CSCNA AN1 VREFL CH0NA CH0NB AN0 AVDD AN3 AVSS S&H1 + - CH123SA CH123SB CH1 AN9(3) VCFG<2:0> ADC1BUF0 VREFL ADC1BUF1 ADC1BUF2 VREFH VREFL CH123NA CH123NB SAR ADC AN1 AN4 S&H2 CH123SA CH123SB CH2 + ADC1BUFE - ADC1BUFF AN10(3) VREFL CH123NA CH123NB AN2 AN5 S&H3 + CH123SA CH123SB
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 19-3: ADC1 BLOCK DIAGRAM FOR PIC24FJXXMC104 DEVICES CTMU TEMP(1) Open(2) AN0-AN12 CTMUI(1) AN15 S&H0 Channel Scan + CH0SA<4:0> CH0 CH0SB<4:0> - CSCNA AN1 VREFL CH0NA CH0NB AN0 AVDD AN3 AVSS S&H1 + - CH123SA CH123SB CH1 AN6 VCFG<2:0> AN9 ADC1BUF0 VREFL ADC1BUF1 ADC1BUF2 VREFH VREFL CH123NA CH123NB SAR ADC AN1 AN4 S&H2 CH123SA CH123SB + ADC1BUFE - ADC1BUFF CH2 AN7 AN10 VREFL CH123NA CH123NB AN2 AN5 S&H3 + CH123SA CH123SB CH3 -
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 19-4: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADxCON3<15> ADC Internal RC Clock(1) 1 TAD ADxCON3<5:0> 0 6 TOSC(1) X2 TCY ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 64 Note 1: 19.3 1. 2. 3. See the ADC specifications in Section 26.0 “Electrical Characteristics” for the exact RC clock value. ADC Helpful Tips 19.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 ADON — ADSIDL — — — R/W-0 R/W-0 FORM<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 SSRC<2:0> U-0 R/W-0 R/W-0 R/W-0 HC,HS R/C-0 HC, HS — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: HC = Cleared by hardware HS = Set by hardware C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 19-1: bit 0 AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed 0 = ADC conversion not started or in progress Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 19-2: R/W-0 AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 VCFG<2:0> U-0 U-0 R/W-0 — — CSCNA R/W-0 R/W-0 CHPS<1:0> bit 15 bit 8 R-0 U-0 BUFS — R/W-0 R/W-0 R/W-0 R/W-0 SMPI<3:0> R/W-0 R/W-0 BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Converter Voltage Reference Configura
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 19-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMC<4:0>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 19-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NB<1:0> R/W-0 CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NA<1:0> R/W-0 CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bi
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 19-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER R/W-0 CH0NB bit 15 U-0 — R/W-0 CH0NA bit 7 U-0 — bit 14-13 bit 12-8 bit 7 bit 6-5 bit 4-0 Note 1: 2: 3: R/W-0 R/W-0 R/W-0 CH0SB<4:0> R/W-0 R/W-0 bit 8 U-0 — R/W-0 R/W-0 R/W-0 CH0SA<4:0> R/W-0 R/W-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 U-0 — W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CH0NB: Chan
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 ,2 REGISTER 19-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2,3) R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS15(4) — — CSS12(4) CSS11(4) CSS10(6) CSS9(6) CSS8(4) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS7(4) CSS6(4) CSS5(5) CSS4(5) CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 19-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3) R/W-0 U-0 U-0 PCFG15(4,5) — — R/W-0 R/W-0 PCFG12(4,5) PCFG11(4,5) R/W-0 R/W-0 R/W-0 PCFG10(4,7) PCFG9(4,7) PCFG8(4,5) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG(4,5) PCFG6(4,5) PCFG5(4,6) PCFG4(4,6) PCFG3(4) PCFG2(4) PCFG1(4) PCFG0(4) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 204 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 20.0 COMPARATOR MODULE Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 48. “Comparator with Blanking” (DS39741) of the “PIC24F Family Reference Manual”, which is available from the Microchip website (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 20-1: COMPARATOR I/O OPERATING MODES EVPOL<1:0> INTREF C1INB MUX C1INC VIN- C1IND VIN+ CVREFIN CPOL – C1 + Interrupt Logic Blanking Function (Figure 20-3) C1OUT COUT MUX C1INA EVPOL<1:0> INTREF C2INB MUX C2INC VIN- C2IND VIN+ CVREFIN CPOL – + C2 Interrupt Logic C2OUT COUT EVPOL<1:0> INTREF C3INB MUX C3INC VIN- C3IND VIN+ CVREFIN CPOL – + C3 Interrupt Logic COE Digital Filter (Figure 20-4) Blanking Function (Figure 20-3)
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 20-2: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRCON<3:0> CVRSRC VREFSEL CVR3 CVR2 CVR1 CVR0 DD(1) AV 8R CVREFIN R CVREN R 16-to-1 MUX R R 16 Steps CVREF R CVRCON R R CVRR 8R Note 1: AVSS(1) FIGURE 20-3: This pin is VDD and VSS on devices that have no AVDD or AVSS pins.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 20-4: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM Timer2 Timer3 PWM Special Event Trigger FOSC FCY ÷CFDIV CFLTREN CFSEL<2:0> From Blanking Logic Digital Filter CXOUT DS39997C-page 208 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 20-1: R/W-0 CMSIDL bit 15 U-0 — CMSTAT: COMPARATOR STATUS REGISTER U-0 — U-0 — U-0 — U-0 — R-0 C3EVT R-0 C2EVT R-0 C1EVT bit 8 U-0 — U-0 — U-0 — U-0 — R-0 C3OUT R-0 C2OUT R-0 C1OUT bit 0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-11 bit 10 bit 9 bit 8 bit 7-3 bit 2 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CMSIDL: Stop in Idle Mode bit 1 = Discon
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 20-2: CMxCON: COMPARATOR CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 CON COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 EVPOL<1:0> U-0 R/W-0 U-0 U-0 — CREF — — R/W-0 R/W-0 CCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator Enable bit 1 = Comparator i
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 20-2: CMxCON: COMPARATOR CONTROL REGISTER (CONTINUED) bit 5 Unimplemented: Read as ‘0’ bit 4 CREF: Comparator Reference Select bit (VIN+ input) 1 = VIN+ input connects to internal CVREFIN voltage 0 = VIN+ input connects to CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = VIN- input of comparator connects to INTREF 10 = VIN- input of comparator connects to CXIND pin 01 = VIN- input of comparator
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 20-3: CMxMSKSRC: COMPARATOR MASK SOURCE SELECT CONTROL REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 RW-0 SELSRCC<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SELSRCB<3:0> R/W-0 R/W-0 R/W-0 SELSRCA<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SELSRCC<3:0>: Mas
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 20-3: bit 3-0 CMxMSKSRC: COMPARATOR MASK SOURCE SELECT CONTROL REGISTER SELSRCA<3:0>: Mask A Input Select bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM1H3 0100 = PWM1L3 0011 = PWM1H2 0010 = PWM1L2 0001 = PWM1H1 0000 = PWM1L1 © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 20-4: CMxMSKCON: COMPARATOR MASK GATING CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 20-4: CMxMSKCON: COMPARATOR MASK GATING CONTROL REGISTER bit 2 ABNEN: AND Gate A1 B Input Inverted Enable bit 1 = Inverted MBI is connected to AND gate 0 = Inverted MBI is not connected to AND gate bit 1 AAEN: AND Gate A1 A Input Enable bit 1 = MAI is connected to AND gate 0 = MAI is not connected to AND gate bit 0 AANEN: AND Gate A1 A Input Inverted Enable bit 1 = Inverted MAI is connected to AND gate 0 = Inverted MAI is not connected to AND gat
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 20-5: CMxFLTR: COMPARATOR FILTER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 I-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 — R/W-0 R/W-0 CFSEL<2:0> R/W-0 CFLTREN R/W-0 R/W-0 R/W-0 CFDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CFSEL<2:0>: Comparator Filter Input C
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 20-6: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — VREFSEL R/W-0 R/W-0 BGSEL<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 CVREN CVROE(1) CVRR — R/W-0 R/W-0 R/W-0 R/W-0 CVR<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 218 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 21.0 REAL-TIME CLOCK AND CALENDAR (RTCC) This chapter discusses the Real-Time Clock and Calendar (RTCC) module, which is available on PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 devices, and its operation. Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 21.1 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 21.1.1 By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR<1:0> bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 21-1: R/W-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) U-0 (2) RTCEN — R/W-0 RTCWREN R-0 RTCSYNC R-0 R/W-0 (3) HALFSEC R/W-0 RTCOE R/W-0 RTCPTR<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable b
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 21-1: bit 7-0 Note 1: 2: 3: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute • • • 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute • • • 10000000 = Maximum negative adjust
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 21-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — U-0 — U-0 — U-0 R/W-0 (1) RTSECSEL bit 7 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = R
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 21-3: R/W-0 ALRMEN bit 15 R/W-0 ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 CHIME R/W-0 R/W-0 R/W-0 AMASK<3:0> R/W-0 R/W-0 R/W-0 ALRMPTR<1:0> bit 8 R/W-0 R/W-0 R/W-0 R/W-0 ARPT<7:0> R/W-0 R/W-0 R/W-0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9-8 bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ALRMEN: Alarm Enable bit 1 = Al
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 21-4: RTCVAL (WHEN RTCPTR<1:0> = 11): YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN<3:0> R/W-x R/W-x YRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN<3:0>: Bin
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 21-6: RTCVAL (WHEN RTCPTR<1:0> = 01): WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 — — — — — R/W-x R/W-x R/W-x WDAY<2:0> bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x HRTEN<1:0> R/W-x R/W-x R/W-x HRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 21-8: ALRMVAL (WHEN ALRMPTR<1:0> = 10): ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x — — — MTHTEN0 R/W-x R/W-x R/W-x R/W-x MTHONE<3:0> bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x R/W-x DAYTEN<1:0> R/W-x R/W-x DAYONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 21-10: ALRMVAL (WHEN ALRMPTR<1:0> = 00): ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x — R/W-x R/W-x R/W-x MINTEN<2:0> R/W-x R/W-x R/W-x MINONE<3:0> bit 15 bit 8 U-0 R/W-x — R/W-x R/W-x R/W-x SECTEN<2:0> R/W-x R/W-x R/W-x SECONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 22.0 CHARGE TIME MEASUREMENT UNIT (CTMU) Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724) in the “PIC24F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 22-1: CTMU BLOCK DIAGRAM CTMUCON1 or CTMUCON2 CTMUICON ITRIM<5:0> IRNG<1:0> Current Source Edge Control Logic CTED1 CTED2 EDG1STAT EDG2STAT TGEN Current Control CTMU Control Logic Analog-to-Digital Trigger Pulse Generator CTPLS Timer1 OC1 IC1 CMP2 CTMUI to ADC CTMUP CTMU TEMP CTMU Temperature Sensor C2INB- CDelay Comparator 2 External capacitor for pulse generation Current Control Selection DS39997C-page 230 TGEN EDG1STAT, EDG2STAT CTM
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 22-1: CTMUCON1: CTMU CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN(2) CTTRIG bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Modu
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 22-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 EDG1MOD EDG1POL R/W-0 R/W-0 R/W-0 R/W-0 EDG1SEL<3:0> R/W-0 R/W-0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 EDG2MOD EDG2POL R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — EDG2SEL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 EDG1MOD: Edge 1 Edge
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 22-3: R/W-0 CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM<5:0> R/W-0 IRNG<1:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Nominal current output specified by IRNG<1
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 234 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 23.0 SPECIAL FEATURES 23.1 Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer (WDT)” (DS39697) and Section 33. “Programming and Diagnostics” (DS39716) in the “PIC24F Family Reference Manual”, which are available from the Microchip web site (www.microchip.
TABLE 23-1: CONFIGURATION SHADOW REGISTER MAP File Name Address Bit 7 Bit 6 Bit 5 Bit 4 — FGS F80004 — — — FOSCSEL F80006 IESO PWMLOCK — FOSC F80008 FWDT F8000A FPOR FICD Legend: Note 1: 2: FCKSM<1:0> Bit 3 Bit 2 — — WDTWIN<1:0> IOL1WAY — PLLKEN WDTPRE Bit 1 Bit 0 GCP GWRP FNOSC<2:0> — OSCIOFNC FWDTEN WINDIS F8000C PWMPIN HPOL LPOL ALTI2C1 — — F8000E Reserved(1) — Reserved(2) Reserved(2) — — POSCMD<1:0> WDTPOST<3:0> — — ICS<1:0> — = unimplemented, rea
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 23-4: PIC24F CONFIGURATION BITS DESCRIPTION Bit Field Description GCP General Segment Code-Protect bit 1 = User program memory is not code-protected 0 = Code protection is enabled for the entire program memory space GWRP General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the u
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 23-4: PIC24F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Description WDTPOST<3:0> Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • PLLKEN ALTI2C ICS<1:0> PWMPIN HPOL LPOL DS39997C-page 238 0001 = 1:2 0000 = 1:1 PLL Lock Enable bit 1 = Clock switch to PLL will wait until the PLL lock signal is valid 0 = Clock switch will not wait for the PLL lock signal Alternate I2C pins 1 = I2C™ mapped to SDA1/SCL1 pins 0 = I2C map
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 REGISTER 23-1: R DEVID: DEVICE ID REGISTER R R R R DEVID<23:16> R R R bit 23 bit 16 R R R R R DEVID<15:8> R R R bit 15 bit 8 R R R R R R R R DEVID<7:0> bit 7 bit 0 Legend: R = Read-Only bit bit 23-0 Note 1: DEIDV<23:0>: Device Identifier bits Refer to the “PIC24FJXXMC Family Flash Programming Specification” (DS70512) for the list of device ID values.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 23.2 On-Chip Voltage Regulator 23.3 All of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 family incorporate an onchip regulator that allows the device to run its core logic from VDD.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 23.4 Watchdog Timer (WDT) 23.4.2 For PIC24FJ16MC101/102 and PIC24FJ32MC101/ 102/104 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 23.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 23.5 In-Circuit Serial Programming 23.6 The PIC24FJ16MC101/102 and PIC24FJ32MC101/ 102/104 devices can be serially programmed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence. Serial programming allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 24.0 INSTRUCTION SET SUMMARY Note 1: This data sheet summarizes the features of the PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest family reference sections of the “PIC24F Family Reference Manual”, which are available from the Microchip web site (www.microchip.com).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Most instructions are a single word. Certain doubleword instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Wm*Wm Description Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wn One of 16 working registers ∈ {W0..W15} Wnd One of 16 destination working registers ∈ {W0...W15} Wns One of 16 source working registers ∈ {W0...
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW Assembly Syntax # of # of Words Cycles Description Status Flags Affected ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z OA
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTG BTSC BTSS BTST BTSTS CALL CLR Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DEC2 Assembly Syntax # of # of Words Cycles Description Status Flags Affected DEC2 f f=f–2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MUL NEG NOP POP Assembly Syntax # of # of Words Cycles Status Flags Affected MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) 1 1 None MUL.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of # of Words Cycles Status Flags Affected SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,S
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 25.0 DEVELOPMENT SUPPORT ® 25.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 25.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 25.7 MPLAB SIM Software Simulator 25.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 26.0 Note: ELECTRICAL CHARACTERISTICS It is important to note that the specifications in this chapter of the data sheet, supercede any specifications that may be provided in PIC24F Family Reference Manual sections. This section provides an overview of PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 26.1 DC Characteristics TABLE 26-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range (in Volts) Characteristic DC5 Note 1: Temp Range (in °C) PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 VBOR-3.6V(1) -40°C to +85°C 16 VBOR-3.6V(1) -40°C to +125°C 16 Overall functional device operation at VBOR < VDD < VDDMIN is guaranteed but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units 3.0 — 3.6 V Conditions Operating Voltage DC10 VDD Supply Voltage(3) (2) Industrial and Extended DC12 VDR RAM Data Retention Voltage 1.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) – PIC24FJ16MC101/102 Devices DC20d 0.7 1.7 mA -40°C DC20a 0.7 1.7 mA +25°C DC20b 1.0 1.7 mA +85°C DC20c 1.3 1.7 mA +125°C DC21d 1.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) – PIC24FJ32MC101/102/104 Devices DC20d 1.7 — mA -40°C DC20a 1.7 — mA +25°C DC20b 1.7 — mA +85°C DC20c 1.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE): Core OFF Clock ON Base Current(2) – PIC24FJ16MC101/102 Devices DC40d 0.6 1.6 mA -40°C DC40a 0.6 1.6 mA +25°C DC40b 0.9 1.6 mA +85°C DC40c 1.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE): Core OFF Clock ON Base Current(2) – PIC24FJ32MC101/102/104 Devices DC40d 1.6 — mA -40°C DC40a 1.6 — mA +25°C DC40b 1.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-9: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Doze Ratio(2) Units Conditions Doze Current (IDOZE)(2) – PIC24FJ16MC101/102 Devices DC73a 13.2 17.2 1:2 mA DC73f 4.7 DC73g 4.7 6.2 1:64 mA 6.2 1:128 mA DC70a 13.2 DC70f 4.7 17.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units VSS — 0.2 VDD V Conditions Input Low Voltage DI10 I/O pins DI15 MCLR VSS — 0.2 VDD V DI18 I/O Pins with SDAx, SCLx VSS — 0.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. DO10 DO20 VOL VOH Characteristic Min Typ Max Units Conditions Output Low Voltage I/O Pins: 4x Sink Driver Pins - All pins excluding OSCO — — 0.4 V IOL ≤ 6 mA, VDD = 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic(3) Min Typ(1) Max Units 10,000 — — E/W Conditions Program Flash Memory D130a EP Cell Endurance D131 VPR VDD for Read VMIN — 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 26.2 AC Characteristics and Timing Parameters This section defines PIC24FJ16MC101/102 and PIC24FJ32MC101/102/104 AC characteristics and timing parameters. TABLE 26-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in Section 26.1 “DC Characteristics”.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 OS30 OS30 Q3 Q4 OSC1 OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 26-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-17: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions PLL Voltage Controlled 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 26-1 for load conditions. TABLE 26-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 26-1 for load conditions. TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 26-1 for load conditions. TABLE 26-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-23: TIMER2/4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 26-1 for load conditions. TABLE 26-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC10 OC11 Note: Refer to Figure 26-1 for load conditions. TABLE 26-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-9: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA1 MP20 PWMx Note 1: See Note 1 For the logic state after a Fault, refer to the FAOVxH:FAOVxL bits in the PxFLTACON register. FIGURE 26-10: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 26-1 for load conditions. TABLE 26-28: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY FOR PIC24FJ16MC101/102 Standard Operating Conditions: 2.4V to 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING CHARACTERISTICS FOR PIC24FJ16MC101/102 SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx LSb SP30, SP31 Note: Refer to Figure 26-1 for load conditions. TABLE 26-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS FOR PIC24FJ16MC101/102 Standard Operating Conditions: 2.4V to 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS FOR PIC24FJ16MC101/102 SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 26-1 for load conditions.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS FOR PIC24FJ16MC101/102 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SDIx LSb SP30, SP31 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 26-1 for load conditions.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS FOR PIC24FJ16MC101/102 SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP51 Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS39997C-page 282 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS FOR PIC24FJ16MC101/102 Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS FOR PIC24FJ16MC101/102 SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP51 Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS39997C-page 284 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS FOR PIC24FJ16MC101/102 Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-17: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS FOR PIC24FJ16MC101/102 SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS39997C-page 286 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS FOR PIC24FJ16MC101/102 Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS FOR PIC24FJ16MC101/102 SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS39997C-page 288 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS FOR PIC24FJ16MC101/102 Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-37: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY FOR PIC24FJ32MC101/102/104 Standard Operating Conditions: 3.0V to 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-20: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING CHARACTERISTICS FOR PIC24FJ32MC101/102/104 SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx LSb SP30, SP31 Note: Refer to Figure 26-1 for load conditions. TABLE 26-38: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS FOR PIC24FJ32MC101/102/104 Standard Operating Conditions: 3.0V to 3.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-21: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS FOR PIC24FJ32MC101/102/104 SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 26-1 for load conditions.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-22: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS FOR PIC24FJ32MC101/102/104 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SDIx LSb SP30, SP31 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 26-1 for load conditions.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-23: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS FOR PIC24FJ32MC101/102/104 SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP51 Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS39997C-page 294 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-41: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS FOR PIC24FJ32MC101/102/104 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-24: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS FOR PIC24FJ32MC101/102/104 SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP51 Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS39997C-page 296 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-42: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS FOR PIC24FJ32MC101/102/104 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-25: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS FOR PIC24FJ32MC101/102/104 SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS39997C-page 298 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-43: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS FOR PIC24FJ32MC101/102/104 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-26: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS FOR PIC24FJ32MC101/102/104 SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. DS39997C-page 300 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-44: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS FOR PIC24FJ32MC101/102/104 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-27: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 26-1 for load conditions. FIGURE 26-28: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 26-1 for load conditions.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-45: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-29: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 26-30: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS39997C-page 304 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-46: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param. Symbol IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 IS40 IS45 IS50 Characteristic Min Max Units 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-47: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Standard Operating Conditions (see Note 6): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Min. Typ Max. Units Module VDD Supply(2,4) Greater of VDD – 0.3 or 2.9 — Lesser of VDD + 0.3 or 3.6 V VSS – 0.3 — VSS + 0.3 V — 7.0 9.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-48: 10-BIT ADC MODULE SPECIFICATIONS Standard Operating Conditions (see Note 4): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 FIGURE 26-31: ADC CONVERSION TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 AD55 TSAMP AD55 DONE ADxIF 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 46.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-49: 10-BIT ADC CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-50: COMPARATOR TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE 26-54: CTMU CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Param No. Symbol Standard Operating Conditions:3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Min. Typ. Max. Units Conditions CTMU CURRENT SOURCE CTMUI1 IOUT1 Base Range — 550 — na IRNG<1:0> bits (CTMUICON<9:8>) = 01 CTMUI2 IOUT2 10x Range — 5.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 312 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 20-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP PIC24FJ16MC 101-E/P e3 0730235 Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 20-Lead SOIC (.300”) PIC24FJ16 MC101-ISS e3 0730235 Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX PIC24FJ16 MC101-ISO e3 0610017 YYWWNNN Legend: XX...
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 27.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 27.1 Package Marking Information (Continued) 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead TQFP PIC24FJ32MC e3 104-E/ML 0730235 Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead VTLA PIC24FJ 32MC104 -E/PT e3 0730235 Example XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 27.
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PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39997C-page 318 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV L 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO :LGW
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39997C-page 320 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .
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PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e b h α h c φ A2 A L A1 Units Dimension Limits Number of Pins β L1 MILLMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 2.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.
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PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39997C-page 328 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS39997C-page 330 Preliminary © 2011-2012 Microchip Technology Inc.
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PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39997C-page 332 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39997C-page 334 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 APPENDIX A: REVISION HISTORY Revision B (June 2011) This revision includes the following global updates: Revision A (February 2011) • All JTAG references have been removed This is the initial released version of the document. All other major changes are referenced by their respective section in Table A-1. In addition, minor text and formatting changes were incorporated throughout the document.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 23.0 “Special Features” Update Description Updated bits 5 and 4 of FPOR, modified Note 2, and removed Note 3 from the Configuration Shadow Register Map (see Table 23-1). Updated bit 14 of CONFIG1 and removed Note 4 from the Configuration Flash Words (see Table 23-2). Updated the PLLKEN Configuration bit description (see Table 23-3).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Revision C (June 2012) This revision includes updates in support of the following new devices: • PIC24FJ32MC101 • PIC24FJ32MC102 • PIC24FJ32MC104 Also, where applicable, new sections were added to peripheral chapters that provide information and links to the related resources, as well as helpful tips. For examples, see Section 18.1 “UART Helpful Tips” and Section 18.2 “UART Resources”.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 7.0 “Interrupt Controller” Update Description Updated the Interrupt Vectors (see Table 7-1). The following registers were updated or added: • Register 7-5: IFS0: Interrupt Flag Status Register 0 • Register 7-11: IEC1: Interrupt Enable Control Register 1 • Register 7-21: IPC6: Interrupt Priority Control Register 6 Section 9.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 26.0 “Electrical Characteristics” Update Description Updated the Absolute Maximum Ratings. Updated TABLE 26-2: Thermal Operating Conditions. Updated TABLE 26-6: DC Characteristics: Operating Current (Idd). Updated TABLE 26-7: DC Characteristics: Idle Current (Iidle). Updated TABLE 26-8: DC Characteristics: Power-Down Current (Ipd). Updated TABLE 26-9: DC Characteristics: Doze Current (Idoze).
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 340 Preliminary © 2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 INDEX A AC Characteristics ............................................................ 268 Internal Fast RC (FRC) Accuracy ............................. 270 Internal Low-Power RC (LPRC) Accuracy ................ 270 Load Conditions ........................................................ 268 ADC Initialization ............................................................... 191 Key Features.............................................................
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 Other Instructions........................................................ 55 Instruction Set Overview ................................................................... 246 Summary................................................................... 243 Instruction-Based Power-Saving Modes ........................... 109 Idle ............................................................................ 110 Sleep ...................................................
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 IPC14 (Interrupt Priority Control 14) ........................... 95 IPC15 (Interrupt Priority Control 15) ........................... 96 IPC16 (Interrupt Priority Control 16) ........................... 97 IPC19 (Interrupt Priority Control 19) ........................... 98 IPC2 (Interrupt Priority Control 2) ............................... 90 IPC3 (Interrupt Priority Control 3) ............................... 91 IPC4 (Interrupt Priority Control 4) ............
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 I2Cx Bus Data Requirements (Slave Mode) ............. 305 Motor Control PWM Requirements ........................... 277 Output Compare Requirements ................................ 276 PLL Clock.................................................................. 270 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements.................................................... 272 Simple OC/PWM Mode Requirements ..............
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 16 MC1 02 T E / SP - XXX Examples: a) PIC24FJ16MC102-E/SP: Motor Control PIC24, 16 KB program memory, 28-pin, Extended temperature, SPDIP package.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104 NOTES: DS39997C-page 348 Preliminary © 2011-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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