Datasheet

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
DS39997C-page 238 Preliminary © 2011-2012 Microchip Technology Inc.
WDTPOST<3:0> Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
PLLKEN PLL Lock Enable bit
1 = Clock switch to PLL will wait until the PLL lock signal is valid
0 = Clock switch will not wait for the PLL lock signal
ALTI2C Alternate I
2
C pins
1 = I
2
C™ mapped to SDA1/SCL1 pins
0 = I
2
C mapped to ASDA1/ASCL1 pins
ICS<1:0> ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
PWMPIN Motor Control PWM Module Pin Mode bit
1 = PWM module pins controlled by PORT register at device Reset (tri-stated)
0 = PWM module pins controlled by PWM module at device Reset (configured as output pins)
HPOL Motor Control PWM High Side Polarity bit
1 = PWM module high side output pins have active-high output polarity
0 = PWM module high side output pins have active-low output polarity
LPOL Motor Control PWM Low Side Polarity bit
1 = PWM module low side output pins have active-high output polarity
0 = PWM module low side output pins have active-low output polarity
TABLE 23-4: PIC24F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field Description