Datasheet

© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 19
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
MCLR
I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.
AV
DD P P No Positive supply for analog modules. This pin must be connected at all
times. AVDD is connected to VDD in 28-pin PIC24FJXXMC102 devices. In
all other devices, AV
DD is separated from VDD.
AV
SS P P No Ground reference for analog modules. AVSS is connected to VSS in 28-pin
PIC24FJXXMC102 devices. In all other devices, AVSS is separated from
V
SS.
V
DD P — No Positive supply for peripheral logic and I/O pins.
V
CAP P — No CPU logic filter capacitor connection.
VSS P — No Ground reference for logic and I/O pins.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1
pin on PIC24FJ16MC101 (20-pin) devices.
2: The FLTB1
pin is available in PIC24FJ(16/32)MC102/104 devices only.
3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM faults.
4: This pin is available in PIC24FJ(16/32)MC104 devices only.
5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.