Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 24  2010-2013 Microchip Technology Inc.
FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM
Instruction
Decode &
Control
16
16-Bit ALU
23
23
24
23
Data Bus
16
Divide
Support
ROM Latch
16
RAGU
WAGU
16
16
8
Interrupt
Controller
Data Latch
Data RAM
Address
Latch
Control Signals
to Various Blocks
Program Memory
Data Latch
Address Bus
16
Literal Data
16
16
Hardware
Multiplier
16
To Peripheral Modules
Address Latch
PSV & Table
Data Access
Control Block
PCH
Program Counter
Stack
Control
Logic
Loop
Control
Logic
PCL
Instruction Reg
EA MUX
16 x 16
W Register Array