Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 10  2010-2013 Microchip Technology Inc.
FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode &
Control
16
PCH
16
Program Counter
16-Bit ALU
23
24
Data Bus
16
Divide
Support
16
16
16
8
Interrupt
Controller
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Program Memory
Data Latch
16
Address Bus
Literal Data
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
VDD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
VDDCORE/VCAP
DISVREG
PORTA
(1)
PORTC
(1)
RA<9:0>
RC<9:0>
PORTB
RB<15:0>
Note 1: Not all pins or features are implemented on all device pinout configurations. See Tab l e 1 - 2 for I/O port pin descriptions.
2: BOR and LVD functionality is provided when the on-board voltage regulator is enabled.
3: Peripheral I/Os are accessible through remappable pins.
RP
(1)
RP<25:0>
Comparators
(3)
Timer2/3
(3)
Timer1
RTCC
IC1-5
(3)
10-Bit
PWM/
SPI1/2
(3)
I2C1/2
Timer4/5
(3)
PMP/PSP
OC1-5
(3)
CN1-22
(1)
UART1/2
(3)
LVD
(2)
PCL
Inst Latch
Read AGU
Write AGU
PSV & Table
Data Access
Control Block
Inst Register
EA MUX
A/D