Information

 2009-2013 Microchip Technology Inc. DS80000470H-page 9
PIC24FJ64GA004 FAMILY
19. Module: SPI
In SPIx Slave mode (MSTEN = 0), with the slave
select option enabled (SSEN = 1), the peripheral
may accept transfers regardless of the SSx pin
state. The received data in SPIxBUF will be
accurate but not intended for the device.
Work around
There is a work around using the Peripheral Pin
Select (PPS) feature. One of the external inter-
rupts (INT1 or INT2) can be mapped to the same
pin as the SSx
signal or the SSx signal can be
mapped to a pin with interrupt-on-change (CNx)
functionality. If the SSx
signal changes to low
(active), the interrupt flag will be set.
When an SPIx data received interrupt occurs, the
interrupt flag can be tested. If the interrupt mapped
to SSx
did not occur, discard the data.
Affected Silicon Revisions
20. Module: SPI
When using Enhanced Buffer mode, an interrupt
will not occur if the following conditions exist:
• SPIx Buffer Interrupt mode, SISEL<2:0>
(SPIxSTAT<4:2>), is set to interrupt when the
Shift register is empty (SISEL<2:0> = 101).
• Slave Select mode is enabled (SSEN = 1).
This only occurs when Enhanced mode, Slave
Select mode and interrupt on Shift register empty
are all enabled. In other modes, the interrupt will
work correctly.
Work around
When Slave Select mode is enabled, interrupting
on SPIxSR empty and TX empty will occur at the
same time. Therefore, interrupting on TX FIFO
empty (SISEL<2:0> = 110) can be used as an
alternative to interrupting when the Shift register is
empty (SISEL<2:0> = 101).
Affected Silicon Revisions
A3/
A4
B4 B5 B8
X
A3/
A4
B4 B5
B8
X