Information

PIC24FJ64GA004 FAMILY
DS80000470H-page 8  2009-2013 Microchip Technology Inc.
14. Module: UART
With the auto-baud feature selected, the Sync field
character (0x55) may be loaded into the FIFO as
data.
Work around
To prevent the Sync field character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
Affected Silicon Revisions
15. Module: UART
The auto-baud may miscalculate for certain baud
rates and clock speed combinations, resulting in a
BRG value that is 1 greater or less than the
expected value. When UxBRG is less than 50, this
can result in transmission and reception failures
due to introducing error greater than 1%.
Work around
Test auto-baud calculations at various clock speed
and baud rate combinations that would be used in
applications. If an inaccurate UxBRG value is gen-
erated, manually correct the baud rate in user
code.
Affected Silicon Revisions
16. Module: UART
The UARTx module will not generate consecutive
Break characters. Trying to perform a back-to-
back Break character transmission will cause the
UARTx module to transmit the dummy character
used to generate the first Break character, instead
of transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
Affected Silicon Revisions
17. Module: Output Compare
In PWM mode, the output compare module may
miss a compare event when the Current Duty
Cycle register (OCxRS) value is 0x0000 (0% duty
cycle) and the OCxRS register is updated with a
value of 0x0001. The compare event is only
missed the first time a value of 0x0001 is written to
OCxRS and the PWM output remains low for one
PWM period. Subsequent PWM high and low
times occur as expected.
Work around
If the current OCxRS register value is 0x0000,
avoid writing a value of 0x0001 to OCxRS.
Instead, write a value of 0x0002. In this case, how-
ever, the duty cycle will be slightly different from
the desired value.
Affected Silicon Revisions
18. Module: SPI
When using Enhanced Buffer mode, some
indicator bits may be set at incorrect times:
• For slave transfers, the SRMPT bit
(SPIxSTAT<7>) is set early, after only 7 SCKx
periods.
• For Slave Interrupt modes (SISELx = 5), there
is a one SCKx period delay between the
interrupt event and the SPIxIF bit being set.
• There may be several instruction cycle delays
between the FIFO full or FIFO empty events
and the interrupt flags, or indicator bits being
set.
Work around
None at this time.
Affected Silicon Revisions
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
XXX
X
A3/
A4
B4 B5 B8
X
A3/
A4
B4 B5
B8
X