Information

PIC24FJ64GA004 FAMILY
DS80000470H-page 6  2009-2013 Microchip Technology Inc.
5. Module: Core
On a Brown-out Reset, both the BOR and POR
bits may be set. This may cause the Brown-out
Reset condition to be indistinguishable from the
Power-on Reset.
Work around
None.
Affected Silicon Revisions
6. Module: Core
The PIC24FJ16GA002 and PIC24FJ16GA004
devices have 8K of data RAM implemented
instead of 4K. This will cause the address error
trap not to function for addresses between 2000h
and 27FFh.
Work around
Do not access RAM beyond address 17FFh to
maintain software compatibility with future device
revisions.
Affected Silicon Revisions
7. Module: A/D
The AD1PCFG and AD1CHS registers allow
unimplemented channels to be selected. If these
channels are selected, they will read as if tied to
V
SS. These channels should be disabled.
Work around
Disable channels, AN13 and AN14, in the
AD1PCFG register by ensuring that bits 13 and 14
are cleared.
Ensure that bits 5 and 12 of AD1CHS are main-
tained cleared. If these bits are set, it will cause the
A/D to reference channels AN16-31.
Affected Silicon Revisions
8. Module: A/D
The A/D module will not generate code 511. Any
conversion which should result in 511 normally, will
instead generate 510 or 512.
Work around
None.
Affected Silicon Revisions
9. Module: A/D
With the External Interrupt 0 (INT0) selected to start
an A/D conversion (SSRC<2:0> = 001), the device
may not wake-up from Sleep or Idle mode if more
than one conversion is selected per interrupt
(SMPI<3:0> <> 0000). Interrupts are generated
correctly if the device is not in Sleep or Idle mode.
Work around
Configure the A/D to generate an interrupt after
every conversion (SMPI<3:0> = 0000). Use
another wake-up source, such as the WDT or
another interrupt source, to exit the Sleep or Idle
mode. Alternatively, perform A/D conversions in
Run mode.
Affected Silicon Revisions
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X