Information

PIC24FJ64GA004 FAMILY
DS80000470H-page 4  2009-2013 Microchip Technology Inc.
SPI Master
mode
46. Spurious transmission and reception of null
data on wake-up from Sleep (Master mode).
XXXX
SPI Master
mode
47. Inaccurate SPITBF flag with high clock
divider.
XXX
SPI Framed
modes
48. Framed SPIx modes not supported. X X X X
Core Data SRAM 49. Higher current consumption during SRAM
operations.
XX
I/O Ports PORTA and
PORTB
50. Some I/O pin functions do not work correctly
under certain conditions
XXXX
A/D
Converter
— 51. Once the A/D module is enabled, it may
continue to draw extra current
XXXX
UART TX Interrupt 52. A TX Interrupt may occur before the data
transmission is complete.
XXX
I
2
CSMBus 53. I2C1 may not function when I2C2 is in
SMBus mode.
XXXX
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A3/A4 B4 B5 B8
Note 1: Only those issues indicated in the last column apply to the current silicon revision.