Information

 2009-2013 Microchip Technology Inc. DS80000470H-page 3
PIC24FJ64GA004 FAMILY
RTCC — 24. Write errors to ALCFGRPT register. X
I
2
C Slave mode 25. In Slave mode, ACKSTAT bit state change. X
I
2
C—26. Issues with write operations on I2CxSTAT. X
UART IrDA
®
27. IR baud clock only available during transmit. X
I/O PPS 28. Issues with digital signal priorities with RP12
and RP18.
X
UART UERIF
Interrupt
29. No UERIF flag with multiple errors. X X X X
UART FIFO Error
Flags
30. PERR and FERR are not correctly set for all
bytes in receive FIFO.
XXXX
Core BOR 31. Spontaneous BOR events with low-range
VDD.
XXXX
Core Instruction
Set
32. Loop count errors with REPEAT instruction
and R-A-W stalls.
X
Memory PSV 33. False address error traps at lower boundary
of PSV space.
XXX
RTCC — 34. Decrement of alarm repeat counter under
certain conditions.
XXX
SPI Master
mode
35. SPIF and SPIBEN may become set early
under certain conditions.
X
I
2
C™ Master
mode
36. Module may respond to its own master
transmission as a slave under certain
conditions.
XXXX
I
2
C Slave mode 37. Failure to respond correctly to some
reserved addresses in 10-bit mode.
XXXX
I
2
C—38. TBF flag not cleared under certain
conditions.
X
UART — 39. Erroneous sampling and framing errors
when using two Stop bits.
XXXX
Oscillator SOSC 40. Low-power SOSC unimplemented. X
Voltage
Regulator
— 41. Standby mode not available. X
Core Code-Protect 42. General code protection disables
bootloader functionality.
X
SPIx — 43. Interrupts when SPIx is operating in
Enhanced Buffer mode.
XXXX
UART IrDA
®
44. RXINV bit operation is inverted in IrDA
®
mode
X
Core Doze Mode 45. Instruction execution glitches following
DOZE bit changes.
XXXX
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A3/A4 B4 B5 B8
Note 1: Only those issues indicated in the last column apply to the current silicon revision.