Information

 2009-2013 Microchip Technology Inc. DS80000470H-page 17
PIC24FJ64GA004 FAMILY
46. Module: SPI (Master Mode)
When operating in Enhanced Buffer Master mode,
the module may transmit two bytes or two words of
data with a value of 0h, immediately upon the
microcontroller waking up from Sleep mode. At the
same time, the module “receives” two words or two
bytes of data, also with the value of 0h.
The transmission of null data occurs even if the
Transmit Buffer registers are empty prior to the
microcontroller entering Sleep mode. The
received null data requires that the receive buffer
be read twice to clear the “received” data.
This behavior has not been observed when the
module is operating in any other mode.
Work around
When operating in Enhanced Buffer Master mode,
disable the module (SPIEN = 0) before entering
Sleep mode.
Affected Silicon Revisions
47. Module: SPI (Master Mode)
When operating in Enhanced Buffer Master mode,
the Transmit Buffer Full Status Flag, SPITBF, may
be cleared before all data in the FIFO buffer has
actually been sent. This may result in data being
overwritten before it can be sent.
This has only been observed when the SPIx clock
prescalers are configured for a divider of greater
than 1:4.
This behavior has not been observed when the
module is operating in any other mode.
Work around
Several options are available:
• If possible, use a total clock prescale factor
of 1:4 or less.
• Do not use SPITBF to indicate when new
data can be written to the buffer. Instead,
use the SPIRBF or SPIBEC flags to track
the number of bytes actually transmitted.
• If the SPITBF flag must be used, always
wait at least one-half SPIx clock cycle
before writing to the transmit buffer.
Affected Silicon Revisions
48. Module: SPI (Framed SPIx Modes)
Framed SPIx modes, as described in the device
data sheet, are not supported. When using the
module, verify the FRMEN bit (SPIxCON2<15>) is
cleared.
All other SPIx modes function as described.
Work around
None.
Affected Silicon Revisions
49. Module: Core (Data SRAM)
During any operations to data SRAM
(addresses above the SFR space, starting at
0800h), the device’s baseline current consump-
tion (I
DD) may periodically be higher than
previously specified in the data sheet. This
occurs only with oscillator speeds of 1 MHz or
slower, regardless of the clock mode.
Work around
None.
Affected Silicon Revisions
50. Module: I/O (PORTA and PORTB)
PORTA pin, RA0, may not operate correctly as
an input when the open-drain output is enabled
for PORTB pin, RB0 (ODCB<0>). RA0 will
operate correctly as an output.
Work around
None.
Affected Silicon Revisions
A3/
A4
B4 B5 B8
XXXX
A3/
A4
B4 B5
B8
XX
X
A3/
A4
B4 B5
B8
XXX
X
A3/
A4
B4 B5
B8
XX
A3/
A4
B4 B5
B8
XXX
X