Information

PIC24FJ256GA110 FAMILY

9. Module: 10-Bit High-Speed A/D

Converter

In Register 20-1 (AD1CON1), the descriptions

provided for the various combinations of the

SSRC<2:0> bits (ADCON1<7:5>) are incorrect.

Specifically, while the number and type of trigger

sources are reported correctly, several are

associated with the wrong bit combinations.

The correct order of trigger sources is listed below

(changes in bold).

10. Module: Special Features

In Register 24-3 (CW3), the explanatory text with

Configuration bits, WPFP<8:0> (CW3<8:0>), is

changed to agree with the text of Section 24.4.2

“Code Segment Protection”. The new register

text is as follows (change in bold):

“Designates the 512-byte program code page that

is the boundary of the protected code segment,

starting with Page 0 at the bottom of program

memory.”

bit 7-5 SSRC2:SSRC0: Conversion Trigger Source Select bits

111 = Internal counter ends sampling and starts conversion (auto-convert)

110 = CTMU event ends sampling and starts conversion

101 = Reserved

100 = Timer5 compare ends sampling and starts conversion

011 = Reserved

010 = Timer3 compare ends sampling and starts conversion

001 = Active transition on INT0 pin ends sampling and starts conversion

000 = Clearing SAMP bit ends sampling and starts conversion