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PIC24FJ256GA110 FAMILY
DS80385B-page 8 © 2009 Microchip Technology Inc.
7. Module: Interrupt Controller
In Register 6-4 (INTCON2), bits 4 and 3 of
INTCON2, currently shown as unimplemented,
are in fact implemented as INT4EP and INT3EP,
respectively.
An amended partial version of this register is
shown below (changes in bold).
8. Module: Timer2/3 and Timer4/5
In the bulleted list in the 3rd paragraph of
Section 11.0 “Timer2/3 and Timer4/5”, it is stated
that the ADC event trigger is only associated with
Timer4/5. In fact, the trigger is only associated with
Timer2/3. This is correctly noted in all other
occurrences in the chapter.
REGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2 (PARTIAL REPRESENTATION)
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
ALTIVT DISI — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT4EP INT3EP INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-5 Unimplemented: Read as ‘0’
bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge