Information

PIC24FJ256GA110 FAMILY
DS80385B-page 6 © 2009 Microchip Technology Inc.
4. Module: Pin Diagrams
In the 64-pin device pin diagram on page 2, the
reference to SCK1 on pin 35 is deleted. The
correct complete designation for this pin is “RPI45/
INT0/CN72/RF6”.
The SCK1 function is available only through Periph-
eral Pin Select (PPS), and is not permanently
multiplexed to any one pin on this device.
5. Module: Memory Organization
(SFR Space)
In Table 3-5 of the device data sheet (Interrupt
Controller Register Map), bits 4 and 3 of INTCON2
are incorrectly shown as unimplemented. These
positions are actually implemented as INT4EP and
INT3EP, respectively.
An amended partial version of the table with the
correct footnote is shown in Table 3-5 (additions in
bold).
6. Module: Memory Organization
(SFR Space)
In Table 3-18 of the device data sheet (PORTG
Register Map), the footnote references on the Bit 1
and Bit 0 columns are incorrect. These bits, and
their corresponding I/O channels, are actually
available on 80-pin devices.
An amended version of the table with the correct
footnote is shown in Table 3-18 (additions and
changes in bold).