Datasheet

 2005-2012 Microchip Technology Inc. DS39747F-page 77
PIC24FJ128GA010 FAMILY
REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0
— —PMPIE— — —OC5IE—
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
IC5IE IC4IE IC3IE
— — — SPI2IE SPF2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 PMPIE: Parallel Master Port Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12-10 Unimplemented: Read as ‘0’
bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8 Unimplemented: Read as ‘0’
bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4-2 Unimplemented: Read as ‘0’
bit 1 SPI2IE: SPI2 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled