Datasheet

PIC24FJ128GA010 FAMILY
DS39747F-page 60  2005-2012 Microchip Technology Inc.
TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type Clock Source SYSRST Delay
System Clock
Delay
FSCM
Delay
Notes
POR EC, FRC, FRCDIV, LPRC T
POR + TSTARTUP + TRST ——1, 2, 3
ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6
XT, HS, SOSC T
POR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6
XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6
BOR EC, FRC, FRCDIV, LPRC TSTARTUP + TRST ——2, 3
ECPLL, FRCPLL T
STARTUP + TRST TLOCK TFSCM 2, 3, 5, 6
XT, HS, SOSC TSTARTUP + TRST TOST TFSCM 2, 3, 4, 6
XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK TFSCM 2, 3, 4, 5, 6
MCLR
Any Clock TRST ——3
WDT Any Clock T
RST ——
3
Software Any Clock T
RST ——
3
Illegal Opcode Any Clock T
RST ——
3
Uninitialized W Any Clock T
RST ——
3
Trap Conflict Any Clock T
RST ——
3
Note 1: T
POR = Power-on Reset delay (10 s nominal).
2: T
STARTUP = TVREG (10 s nominal) if the on-chip regulator is enabled or TPWRT (64 ms nominal) if an
on-chip regulator is disabled.
3: T
RST = Internal state Reset time (20 s nominal).
4: T
OST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
5: T
LOCK = PLL lock time.
6: TFSCM = Fail-Safe Clock Monitor delay (100 s nominal).