Datasheet

PIC24FJ128GA010 FAMILY
DS39747F-page 202  2005-2012 Microchip Technology Inc.
24.3 Watchdog Timer (WDT)
For PIC24FJ128GA010 family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (T
WDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS<3:0> Con-
figuration bits (Flash Configuration Word 1<3:0>),
which allow the selection of a total of 16 settings, from
1:1 to 1:32,768. Using the prescaler and postscaler,
time-out periods, ranging from 1 ms to 131 seconds,
can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed (i.e.,
Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
•By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake-up and code execution will con-
tinue from where the PWRSAV instruction was executed.
The corresponding SLEEP or IDLE bits (RCON<3:2>)
will need to be cleared in software after the device
wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
24.3.1 CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN con-
trol bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for crit-
ical code segments and disables the WDT during
non-critical segments for maximum power savings.
FIGURE 24-2: WATCHDOG TIMER (WDT) BLOCK DIAGRAM
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 9. “Watchdog
Timer (WDT)” (DS39697) in the “PIC24F
Family Reference Manual” for more
information.
Note: The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
LPRC Input
WDT Overflow
Wake from Sleep
32 kHz
Prescaler
Postscaler
FWPSA
SWDTEN
FWDTEN
Reset
All Device Resets
Sleep or Idle Mode
LPRC Control
CLRWDT Instr.
PWRSAV Instr.
(5-bit/7-bit)
1:1 to 1:32.768
WDTPS<3:0>
1 ms/4 ms
Exit Sleep or
Idle Mode
WDT
Counter
Transition to
New Clock Source