Datasheet

 2005-2012 Microchip Technology Inc. DS39747F-page 201
PIC24FJ128GA010 FAMILY
24.2 On-Chip Voltage Regulator
All of the PIC24FJ128GA010 family devices power
their core digital logic at a nominal 2.5V. This may
create an issue for designs that are required to operate
at a higher typical voltage, such as 3.3V. To simplify
system design, all devices in the PIC24FJ128GA010
family incorporate an on-chip regulator that allows the
device to run its core logic from V
DD.
The regulator is controlled by the ENVREG pin. Tying
V
DD to the pin enables the regulator, which in turn,
provides power to the core from the other V
DD pins.
When the regulator is enabled, a low-ESR capacitor
(such as tantalum) must be connected to the
V
DDCORE/VCAP pin (Figure 24-1). This helps to main-
tain the stability of the regulator. The recommended
value for the filter capacitor, CEFC, is provided in
Section 27.1 “DC Characteristics”.
If ENVREG is tied to V
SS, the regulator is disabled. In
this case, separate power for the core logic, at a nomi-
nal 2.5V, must be supplied to the device on the
V
DDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the V
DDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 24-1 for possible
configurations.
24.2.1 ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approxi-
mately 20 s for it to generate output. During this time,
designated as T
STARTUP, code execution is disabled.
T
STARTUP is applied every time the device resumes
operation after any power-down, including Sleep mode.
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up.
24.2.2 ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled,
PIC24FJ128GA010 devices also have a simple
brown-out capability. If the voltage supplied to the reg-
ulator is inadequate to maintain a regulated level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON<0>). The brown-out voltage specifications can
be found in the “PIC24F Family Reference Manual” in
Section 7. “Reset” (DS39712).
24.2.3 POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
DDCORE must
never exceed V
DD by 0.3 volts.
FIGURE 24-1: CONNECTIONS FOR THE
ON-CHIP REGULATOR
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24FJ128GA010
3.3V
(1)
2.5V
(1)
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24FJ128GA010
CEFC
3.3V
Regulator Enabled (ENVREG tied to VDD):
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24FJ128GA010
2.5V
(1)
Regulator Disabled (VDD tied to VDDCORE):
Note 1: These are typical operating voltages. Refer
to
Section 27.1 “DC Characteristics” for
the full operating ranges of V
DD and
V
DDCORE.
(10 F typ)