Datasheet

 2005-2012 Microchip Technology Inc. DS39747F-page 177
PIC24FJ128GA010 FAMILY
20.4 Operation in Power Save Modes
20.4.1 SLEEP MODE
If Sleep mode is entered while the module is operating,
the module will be suspended in its current state until
clock execution resumes.
20.4.2 IDLE MODE
To continue full module operation in Idle mode, the
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode. Pending interrupt events will be
passed on, even though the module clocks are not
available.
REGISTER 20-1: CRCCON: CRC CONTROL REGISTER
U-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0
— — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0
bit 15 bit 8
R-0 R-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CRCFUL CRCMPT
— CRCGO PLEN3 PLEN2 PLEN1 PLEN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 CSIDL: CRC Stop in Idle Mode bit
1 = Discontinues module operation when the device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-8 VWORD<4:0>: Pointer Value bits
Indicates the number of valid words in the FIFO. It has a maximum value of 8 when PLEN<3:0> > 7
or 16 when PLEN<3:0>
7.
bit 7 CRCFUL: FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6 CRCMPT: FIFO Empty bit
1 = FIFO is empty
0 = FIFO is not empty
bit 5 Unimplemented: Read as ‘0’
bit 4 CRCGO: Start CRC bit
1 = Starts CRC serial shifter
0 = CRC serial shifter is turned off
bit 3-0 PLEN<3:0>: Polynomial Length bits
Denotes the length of the polynomial to be generated minus 1.