Datasheet

PIC24FJ128GA010 FAMILY
DS39747F-page 154  2005-2012 Microchip Technology Inc.
REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMPEN
— PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0
(1)
R/W-0
(1)
R/W-0
(1)
R/W-0 R/W-0 R/W-0
CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PMPEN: Parallel Master Port Enable bit
1 = PMP is enabled
0 = PMP is disabled, no off-chip access is performed
bit 14 Unimplemented: Read as ‘0’
bit 13 PSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>
00 = Address and data appear on separate pins
bit 10 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port is enabled
0 = PMBE port is disabled
bit 9 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 8 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR
port is enabled
0 = PMRD/PMWR
port is disabled
bit 7-6 CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = PMCS1 and PMCS2 function as chip select
01 = PMCS2 functions as chip select, PMCS1 functions as Address Bit 14
00 = PMCS1 and PMCS2 function as Address Bits 15 and 14
bit 5 ALP: Address Latch Polarity bit
(1)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL
and PMALH)
bit 4 CS2P: Chip Select 2 Polarity bit
(1)
1 = Active-high (PMCS2)
0 =Active-low (PMCS2
)
bit 3 CS1P: Chip Select 1 Polarity bit
(1)
1 = Active-high (PMCS1/PMCS)
0 =Active-low (PMCS1
/PMCS)
Note 1: These bits have no effect when their corresponding pins are used as address lines.