Datasheet

 2005-2012 Microchip Technology Inc. DS39747F-page 141

PIC24FJ128GA010 FAMILY

bit 5 ACKDT: Acknowledge Data bit (When operating as an I

C master; applicable during master receive.)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1 = Sends NACK during Acknowledge

0 = Sends ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit

(When operating as an I

C master; applicable during master receive.)

1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.

Hardware is clear at the end of the master Acknowledge sequence.

0 = Acknowledge sequence is not in progress

bit 3 RCEN: Receive Enable bit (when operating as an I

C master)

1 = Enables Receive mode for I

C. Hardware is clear at the end of the eighth bit of the master receive

data byte.

0 = Receive sequence is not in progress

bit 2 PEN: Stop Condition Enable bit (when operating as an I

C master)

1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of the master Stop

sequence.

0 = Stop condition is not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as an I

C master)

1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of the

master Repeated Start sequence.

0 = Repeated Start condition is not in progress

bit 0 SEN: Start Condition Enable bit (when operating as an I

C master)

1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start

sequence.

0 = Start condition is not in progress