Datasheet
2005-2012 Microchip Technology Inc. DS39747F-page 139
PIC24FJ128GA010 FAMILY
16.2 Setting Baud Rate When
Operating as a Bus Master
To compute the Baud Rate Generator reload value, use
the following equation:
EQUATION 16-1:
(1)
16.3 Slave Address Masking
The I2CxMSK register (Register 16-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond, whether the corresponding
address bit value is a ‘0’ or ‘1’. For example, when
I2CxMSK is set to ‘00100000’, the slave module will
detect both addresses, ‘0000000’ and ‘00100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
TABLE 16-1: I
2
C™ CLOCK RATES
(1,3,4)
As a result of changes in the I
2
C protocol, several I
2
C
addresses are reserved and will not be Acknowledged
in Slave mode.
Address masking does not affect behavior. Refer to
Table 16-2 for a summary of these reserved addresses.
.
Note 1: Based on FCY = FOSC/2; Doze mode and
PLL are disabled.
I2CxBRG = (FCY/FSCL – FCY/10,000,000) – 1
Required
System
FSCL
FCY
I2CxBRG Value
Actual
F
SCL
(Decimal) (Hexadecimal)
100 kHz 16 MHz 157 9D 100 kHz
100 kHz 8 MHz 78 4E 100 kHz
100 kHz 4 MHz 39 27 99 kHz
400 kHz 16 MHz 37 25 404 kHz
400 kHz 8 MHz 18 12 404 kHz
400 kHz 4 MHz 9 9 385 kHz
(2)
400 kHz 2 MHz 4 4 385 kHz
(2)
1 MHz 16 MHz 13 D 1,026 KHz
1MHz 8MHz 6 6 1,026KHz
1MHz 4MHz 3 3 909 KHz
Note 1: Based on T
CY = TOSC * 2; Doze mode and PLL are disabled.
2: This is the closest value to 400 kHz for this value of F
CY.
3: F
CY = 2 MHz is the minimum input clock frequency to have FSCL = 1 MHz.
4: I2CxBRG cannot have a value of less than 2.
TABLE 16-2: RESERVED I
2
C™ ADDRESSES
(1)
Slave Address R/W Bit Description
0000 000 0 General Call Address
(2)
0000 000 1 Start Byte
0000 001 x C
BUS Address
0000 010 x Reserved
0000 011 x Reserved
0000 1xx x HS Mode Master Code
1111 1xx x Reserved
1111 0xx x 10-Bit Slave Upper Byte
(3)
Note 1: The above address bits will not cause an address match, independent of address mask settings.
2: The address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.