Datasheet

PIC24FJ128GA010 FAMILY
DS39747F-page 134  2005-2012 Microchip Technology Inc.
FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE)
FIGURE 15-4: SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
LSb
MSb
SDIx
SDOx
PROCESSOR 2 (SPI Slave)
SCKx
SSx
Serial Transmit Buffer
(SPIxTXB)
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1 (SPI Master)
Serial Clock
(SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0)
Note 1: Using the SSx pin in the Slave mode of operation is optional.
2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
SCKx
Serial Transmit Buffer
(SPIxTXB)
(MSTEN (SPIxCON1<5> = 1))
SPIx Buffer
(SPIxBUF)
SPIx Buffer
(SPIxBUF)
Shift Register
(SPIxSR)
LSb
MSb
SDIx
SDOx
PROCESSOR 2 (SPI Enhanced Buffer Slave)
SCKx
SSx
Shift Register
(SPIxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1 (SPI Enhanced Buffer Master)
Serial Clock
SSEN (SPIxCON1<7>) = 1 and
Note 1: Using the SSx
pin in Slave mode of operation is optional.
2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
SSx
SCKx
8-Level FIFO Buffer
MSTEN (SPIxCON1<5> = 1 and
SPIx Buffer
(SPIxBUF)
8-Level FIFO Buffer
SPIx Buffer
(SPIxBUF)
SPIBEN (SPIxCON2<0>) = 1 MSTEN (SPIxCON1<5>) = 0 and
SPIBEN (SPIxCON2<0>) = 1