Datasheet

 2005-2012 Microchip Technology Inc. DS39747F-page 129
PIC24FJ128GA010 FAMILY
FIGURE 15-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Internal Data Bus
SDIx
SDOx
SSx
/FSYNCx
SCKx
SPIxSR
bit 0
Shift
Control
Edge
Select
F
CY
Primary
1:1/4/16/64
Enable
Prescaler
Secondary
Prescaler
1:1 to 1:8
Sync
SPIxBUF
Control
Transfer
Transfer
Write SPIxBUFRead SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
Clock
Control
Receive Buffer
8-Level FIFO
Transmit Buffer
8-Level FIFO