Datasheet

 2005-2012 Microchip Technology Inc. DS39747F-page 121
PIC24FJ128GA010 FAMILY
14.0 OUTPUT COMPARE
14.1 MODES OF OPERATION
Each output compare module has the following modes
of operation:
• Single Compare Match mode
• Dual Compare Match mode generating:
- Single Output Pulse mode
- Continuous Output Pulse mode
• Simple Pulse-Width Modulation mode:
- with Fault protection input
- without Fault protection input
14.2 Setup for Single Output Pulse
Generation
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
FIGURE 14-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 16. “Output
Compare” (DS39706) in the “PIC24F
Family Reference Manual” for more
information.
Comparator
Output
Logic
QS
R
OCM<2:0>
Output Enable
OCx
(1)
Set Flag bit
OCxIF
(1)
OCxRS
(1)
Mode Select
3
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1
through 5.
2: OCFA pin controls OC1-OC4 channels; OCFB pin controls OC5.
3: Each output compare channel can use either Timer2 or Timer3.
OCTSEL
0
1
1616
OCFA or OCFB
(2)
TMR Register Inputs
from Time Bases
(see Note 3)
Period Match Signals
from Time Bases
(see Note 3)
0
1
OCxR
(1)