Datasheet

 2005-2012 Microchip Technology Inc. DS39747F-page 119
PIC24FJ128GA010 FAMILY
13.0 INPUT CAPTURE
The input capture module has multiple operating
modes, which are selected via the ICxCON register.
The operating modes include:
• Capture timer value on every falling edge of input,
applied at the ICx pin
• Capture timer value on every rising edge of input,
applied at the ICx pin
• Capture timer value on every fourth rising edge of
input, applied at the ICx pin
• Capture timer value on every 16th rising edge of
input, applied at the ICx pin
• Capture timer value on every rising and every
falling edge of input, applied at the ICx pin
• Device wake-up from capture pin during CPU
Sleep and Idle modes
The input capture module has a four-level FIFO buffer.
The number of capture events required to generate a
CPU interrupt can be selected by the user.
FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 15. “Input Cap-
ture” (DS39701) in the “PIC24F Family
Reference Manual” for more information.
ICxBUF
ICx Pin
ICM<2:0> (ICxCON<2:0>)
Mode Select
3
10
Set Flag ICxIF
(in IFSx Register)
TMRx
Edge Detection Logic
16 16
FIFO
R/W
Logic
ICI<1:0>
ICOV, ICBNE (ICxCON<4:3>)
ICxCON
Interrupt
Logic
System Bus
From 16-Bit Timers
ICTMR
(ICxCON<7>)
Prescaler
Counter
(1, 4, 16)
and
Clock Synchronizer
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
TMRy