Datasheet

 2005-2012 Microchip Technology Inc. DS39747F-page 115
PIC24FJ128GA010 FAMILY
FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TCY
TCS
1x
01
TGATE
00
Gate
T2CK
Sync
PR2 (PR4)
Set T2IF (T4IF)
Equal
Comparator
TMR2 (TMR4)
Reset
Q
QD
CK
TGATE
1
0
(T4CK)
Sync
TON
TCKPS<1:0>
2
T
CY
TCS
1x
01
TGATE
00
T3CK
PR3 (PR5)
Set T3IF (T5IF)
Equal
Comparator
TMR3 (TMR5)
Reset
Q
QD
CK
TGATE
1
0
A/D Event Trigger*
(T5CK)
* The A/D Event Trigger is available only on Timer2/3.
Prescaler
1, 8, 64, 256
Sync