Datasheet

PIC24FJ128GA010 FAMILY
DS39747F-page 114  2005-2012 Microchip Technology Inc.
FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TMR3
TMR2
Set T3IF (T5IF)
Equal
Comparator
PR3 PR2
Reset
LSB MSB
Note: The 32-bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
* The A/D Event Trigger is only available on Timer2/3.
Data Bus<15:0>
TMR3HLD
Read TMR2 (TMR4)
Write TMR2 (TMR4)
16
16
16
Q
QD
CK
TGATE
0
1
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
T
CY
TCS
1x
01
TGATE
00
Gate
T2CK
A/D Event Trigger*
Sync
(T4CK)
(PR5) (PR4)
(TMR5HLD)
(TMR5)
(TMR4)
Sync