Datasheet

PIC24FJ128GA010 FAMILY
DS39747F-page 108  2005-2012 Microchip Technology Inc.
10.1.1 OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually con-
figured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than V
DD (e.g., 5V) on any desired
digital only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
IH specification.
10.2 Configuring Analog Port Pins
The use of the AD1PCFG and TRIS registers control
the operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (V
OH or VOL) will be
converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
10.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
10.2.2 ANALOG INPUT PINS AND
VOLTAGE CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are
used as digital only inputs are able to handle DC volt-
ages up to 5.5V, a level typical for digital logic circuits.
In contrast, pins that also have analog input functions
of any kind can only tolerate voltages up to V
DD. On
these pins, voltage excursions beyond V
DD are always
to be avoided. Table 10-1 summarizes the input capa-
bilities. Refer to Section 27.1 “DC Characteristics”
for more details.
EXAMPLE 10-1: PORT WRITE/READ EXAMPLE
Note: For easy identification, the pin diagrams at
the beginning of this data sheet also indi-
cate 5.5V tolerant pins with dark grey
shading.
TABLE 10-1: INPUT VOLTAGE LEVELS
(1)
Port or Pin
Tolerated
Input
Description
PORTA<10:9> V
DD Only VDD input
levels are tolerated.
PORTB<15:0>
PORTC<15:12>
PORTA<15:14> 5.5V Tolerates input
levels above V
DD,
useful for most
standard logic.
PORTA<7:0>
PORTC<4:1>
PORTD<15:0>
PORTE<9:0>
PORTF<13:12>
PORTF<8:0>
PORTG<15:12>
PORTG<9:6>
PORTG<3:0>
Note 1: Not all port pins shown here are imple-
mented on 64-pin and 80-pin devices.
Refer to Section 1.0 “Device Overview”
to confirm which ports are available in
specific devices.
MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs
MOV W0, TRISBB ; and PORTB<7:0> as outputs
NOP ; Delay 1 cycle
btss PORTB, #13 ; Next Instruction