Datasheet

PIC24FJ128GA010 FAMILY
DS39747F-page 10  2005-2012 Microchip Technology Inc.
FIGURE 1-1: PIC24FJ128GA010 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode &
Control
16
PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
PCH
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Program Memory
Data Latch
16
Address Bus
Literal Data
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSC1/CLKI
OSC2/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
VDDCORE/VCAP
ENVREG
UART1/2
Comparators
Timer2/3Timer1
RTCC
IC1-5
A/D
10-Bit
PWM/
SPI1/2
I2C1/2
Timer4/5
PORTA
(1)
PORTC
PORTD
(1)
PORTE
(1)
PORTF
(1)
PORTG
(1)
RA0:RA7,
RC1:RC4,
RD0:RD15
RE0:RE9
RF0:RF8,
RG0:RG9,
PORTB
(1)
RB0:RB15
RA9:RA10,
RA14:15
RC12:RC15
RF12:RF13
RG12:RG15
Note 1: Not all pins or features are implemented on all device pinout configurations. See Ta bl e 1 -2 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
PMP/PSP
OC1-5
CN1-22
(1)