PIC24FJ128GA010 FAMILY 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers High-Performance CPU: Analog Features: • Modified Harvard Architecture • Up to 16 MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier • 32-Bit by 16-Bit Hardware Divider • 16 x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture: - 76 base instructions - Flexible addressing modes • Two Address Ge
PIC24FJ128GA010 FAMILY Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP/QFN(1) PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/VREF-/AN1/CN3/RB1 2 3 4 5 6 7 8 9 10 11 12 PIC2
PIC24FJ128GA010 FAMILY Pin Diagrams (Continued) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 80-Pin TQFP PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T4CK/RC3 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/INT1/RE8 TDO/INT2/RE9 2 3 4 5 6 7 8 9 10 11 12 PIC24FJXXGA008 PIC24FJXXX
PIC24FJ128GA010 FAMILY Pin Diagrams (Continued)) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 RG13 RG12 RG14 PMD1/RE1 PMD0/RE0 RA7 RA6 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC24FJXXGA010 PIC24FJXXXGA010 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
PIC24FJ128GA010 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19 3.0 CPU...................................................................................................
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PIC24FJ128GA010 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • • • • • • • • • PIC24FJ64GA006 PIC24FJ64GA008 PIC24FJ64GA010 PIC24FJ96GA006 PIC24FJ96GA008 PIC24FJ96GA010 PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA010 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ128GA010 family incorporate a range of features that can significantly reduce power consumption during operation.
PIC24FJ128GA010 FAMILY 1.1.4 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 64-pin to 80-pin to 100-pin devices.
PIC24FJ128GA010 FAMILY Operating Frequency PIC24FJ128GA010 PIC24FJ96GA010 PIC24FJ64GA010 PIC24FJ128GA008 DC – 32 MHz Program Memory (Bytes) Program Memory (Instructions) PIC24FJ96GA008 PIC24FJ64GA008 PIC24FJ128GA006 Features PIC24FJ96GA006 DEVICE FEATURES FOR THE PIC24FJ128GA010 FAMILY PIC24FJ64GA006 TABLE 1-1: 64K 96K 128K 64K 96K 128K 64K 96K 128K 22,016 32,768 44,032 22,016 32,768 44,032 22,016 32,768 44,032 Data Memory (Bytes) 8192 Interrupt Sources (Soft Vectors/NMI T
PIC24FJ128GA010 FAMILY FIGURE 1-1: PIC24FJ128GA010 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) RA0:RA7, RA9:RA10, RA14:15 16 16 8 16 Data Latch PSV & Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 PORTB(1) Address Latch RB0:RB15 16 23 16 Read AGU Write AGU Address Latch 16 PORTC RC1:RC4, RC12:RC15 Program Memory Data Latch EA MUX 24 Inst Latch Literal Data Address Bus 16 PORTD(1) 16 RD0:RD15 Inst
PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS Pin Number Function I/O 100-Pin Input Buffer 64-Pin 80-Pin AN0 16 20 25 I ANA AN1 15 19 24 I ANA AN2 14 18 23 I ANA AN3 13 17 22 I ANA AN4 12 16 21 I ANA AN5 11 15 20 I ANA AN6 17 21 26 I ANA AN7 18 22 27 I ANA AN8 21 27 32 I ANA AN9 22 28 33 I ANA Description A/D Analog Inputs.
PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number I/O Input Buffer 50 I ST 80 I ST 47 I ST Function 64-Pin 80-Pin 100-Pin CN18 32 40 CN19 — 65 CN20 — 37 Description Interrupt-on-Change Inputs. CN21 — 38 48 I ST CVREF 23 29 34 O ANA Comparator Voltage Reference Output. EMUC1 15 19 24 I/O ST In-Circuit Emulator Clock Input/Output. EMUD1 16 20 25 I/O ST In-Circuit Emulator Data Input/Output.
PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number I/O Input Buffer 44 I/O ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). 35 43 I/O ST/TTL Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes).
PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number I/O Input Buffer 17 I/O ST 38 I/O ST — 58 I/O ST — 59 I/O ST — — 60 I/O ST RA5 — — 61 I/O ST RA6 — — 91 I/O ST RA7 — — 92 I/O ST RA9 — 23 28 I/O ST RA10 — 24 29 I/O ST RA14 — 52 66 I/O ST RA15 — 53 67 I/O ST RB0 16 20 25 I/O ST RB1 15 19 24 I/O ST RB2 14 18 23 I/O ST RB3 13 17 22 I/O ST RB4 12 16 21 I/O ST RB5 11 1
PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number I/O Input Buffer 72 I/O ST 76 I/O ST 62 77 I/O ST 63 78 I/O ST 52 66 81 I/O ST RD5 53 67 82 I/O ST RD6 54 68 83 I/O ST RD7 55 69 84 I/O ST RD8 42 54 68 I/O ST RD9 43 55 69 I/O ST ST Function 64-Pin 80-Pin 100-Pin RD0 46 58 RD1 49 61 RD2 50 RD3 51 RD4 RD10 44 56 70 I/O RD11 45 57 71 I/O ST RD12 — 64 79 I/O ST RD13 — 65 80 I/
PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function I/O 64-Pin 80-Pin 100-Pin Input Buffer RG0 — 75 90 I/O ST RG1 — 74 89 I/O ST RG2 37 47 57 I/O ST RG3 36 46 56 I/O ST RG6 4 6 10 I/O ST RG7 5 7 11 I/O ST Description PORTG Digital I/O.
PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number I/O Input Buffer 47 I ST Function U1CTS 64-Pin 80-Pin 100-Pin 43 37 Description UART1 Clear-to-Send Input. U1RTS 35 38 48 O — UART1 Request-to-Send Output. U1RX 34 42 52 I ST UART1 Receive. U1TX 33 41 51 O DIG UART1 Transmit Output. U2CTS 21 27 40 I ST UART2 Clear-to-Send Input. U2RTS 29 35 39 O — UART2 Request-to-Send Output.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 18 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24F J devices only) (see Section 2.
PIC24FJ128GA010 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24FJ128GA010 FAMILY 2.4 Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) Note: This section applies only to PIC24F J devices with an on-chip voltage regulator. The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground.
PIC24FJ128GA010 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PIC24FJ128GA010 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24FJ128GA010 FAMILY 2.7 Configuration of Analog and Digital Pins During ICSP Operations If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins. Depending on the particular device, this is done by setting all bits in the ADnPCFG register(s), or clearing all bit in the ANSx registers. All PIC24F devices will have either one or more ADnPCFG registers or several ANSx registers (one for each port); no device will have both.
PIC24FJ128GA010 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 2. “CPU” (DS39703) in the “PIC24F Family Reference Manual” for more information. The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, and a 24-bit instruction word with a variable length opcode field.
PIC24FJ128GA010 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 23 PCL PCH Program Counter Loop Stack Control Control Logic Logic 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory EA MUX Address Bus Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction Reg Hardware Multiplier Divide Support 16 Literal Data Instruction Decode & Control 16 16 x 16 W Registe
PIC24FJ128GA010 FAMILY TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register PSVPAG Program Space Visibility Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 W
PIC24FJ128GA010 FAMILY 3.
PIC24FJ128GA010 FAMILY REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — R/C-0 (1) IPL3 R/W-0 U-0 U-0 PSV — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Pri
PIC24FJ128GA010 FAMILY 3.3 Arithmetic Logic Unit (ALU) The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
PIC24FJ128GA010 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. 4.1 Program Address Space The program address memory space of PIC24FJ128GA010 family devices is 4M instructions.
PIC24FJ128GA010 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In PIC24FJ128GA010 family devices, the top two words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ128GA010 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in Figure 4-1.
PIC24FJ128GA010 FAMILY 4.2 Note: Data Address Space This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 3. “Data Memory” (DS39717) in the “PIC24F Family Reference Manual” for more information. The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations.
PIC24FJ128GA010 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT A Sign-Extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations.
2005-2012 Microchip Technology Inc.
INTERRUPT CONTROLLER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 INTCON1 0080 NSTDIS — — — — — — — — — — INTCON2 0082 ALTIVT DISI — — — — — — — — — IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — Bit 4 Bit 3 MATHERR ADDRERR Bit 2 Bit 1 Bit 0 All Resets STKERR OSCFAIL — 0000 INT3EP INT2EP INT1E
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File Name Addr IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 IC3BUF 0148 IC3CON 014A IC4BUF 014C IC4CON 014E IC5BUF 0150 IC5CON 0152 INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 Input 1 Capture Register — ICTMR xxxx Input 2 Capture Register — — ICSIDL — — — — — ICTMR — ICSIDL — — — — — ICI1 ICTMR
2005-2012 Microchip Technology Inc.
File Name Addr UART1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK Bit 0 All Resets Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 ADDEN RIDLE PERR FERR OERR URXDA 0110 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U1STA 0222 UTXISEL1 TXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT U1TXREG 0224 — — — — — — — Transmit Register xxxx U1RXREG 0226 — — — — — — — Receive Re
2005-2012 Microchip Technology Inc.
File Name PORTB REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 TRISB13(1) TRISB12(1) TRISB11(1) TRISB10(1) Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISB 02C6 TRISB15 TRISB14 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF PORTB 02C8 RB15 RB14 RB13(1) RB12(1) RB11(1) RB10(1) RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CA LATB15 LATB14 LATB13(1) LATB12(1) LATB11(1) LATB1
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File Name PARALLEL MASTER/SLAVE PORT REGISTER MAP Addr Bit 15 PMCON 0600 PMPEN — PSIDL PMMODE 0602 BUSY IRQM1 IRQM0 CS2 CS1 PMADDR(1) PMDOUT1(1) 0604 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN INCM1 INCM0 MODE16 MODE1 MODE0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 Parallel Port Destination Address<
2005-2012 Microchip Technology Inc. TABLE 4-27: File Name CRC REGISTER MAP Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 0000 Bit 15 Bit 14 Bit 13 CRCCON 0640 — — CSIDL CRCXOR 0642 CRC XOR Polynomial Register CRCDAT 0644 CRC Data Input Register 0000 CRCWDAT 0646 CRC Result Register 0000 Legend: Bit 12 Bit 5 Addr VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT 0000 — = unimplemented, read as ‘0’.
PIC24FJ128GA010 FAMILY 4.2.5 SOFTWARE STACK 4.3 In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and postincrements for stack pushes, as shown in Figure 4-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.
PIC24FJ128GA010 FAMILY TABLE 4-31: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 PSVPAG<7:0> Data EA<14:0>(1)
PIC24FJ128GA010 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
PIC24FJ128GA010 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 50 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 5.0 controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. FLASH PROGRAM MEMORY Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 4. “Program Memory” (DS39715) in the “PIC24F Family Reference Manual” for more information. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions.
PIC24FJ128GA010 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.
PIC24FJ128GA010 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 R/W-0(1) U-0 — U-0 ERASE — U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR:
PIC24FJ128GA010 FAMILY 5.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data.
PIC24FJ128GA010 FAMILY EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0,
PIC24FJ128GA010 FAMILY 5.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be programmed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes of the Flash address. The TBLWTL and TBLWTH EXAMPLE 5-4: instructions write the desired data into the write latches and specify the lower 16 bits of the program memory address to write to.
PIC24FJ128GA010 FAMILY 6.0 Note: RESETS Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 7. “Reset” (DS39712) in the “PIC24F Family Reference Manual” for more information. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A POR will clear all bits except for the BOR and POR bits (RCON<1:0>), which are set.
PIC24FJ128GA010 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 TRAPR bit 15 R/W-0 IOPUWR U-0 — U-0 — U-0 — U-0 — R/W-0 CM R/W-0 VREGS bit 8 R/W-0 EXTR bit 7 R/W-0 SWR R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1 BOR R/W-1 POR bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: 2: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is u
PIC24FJ128GA010 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 6-1: bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (note that BOR is also set after a Power-on Reset) 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred bit 0 Note 1: 2: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
PIC24FJ128GA010 FAMILY TABLE 6-3: Reset Type RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Clock Source SYSRST Delay EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST POR BOR System Clock Delay FSCM Delay — — Notes 1, 2, 3 ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6 XTPLL, HSPLL 1, 2, 3, 4, 5, 6 TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM EC, FRC, FRCDIV, LPRC TSTARTUP + TRST — — 2, 3 ECPLL, FRCPLL TSTARTU
PIC24FJ128GA010 FAMILY 6.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 62 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 8. “Interrupts” (DS39707) in the “PIC24F Family Reference Manual” for more information. The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU.
PIC24FJ128GA010 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap V
PIC24FJ128GA010 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Source ADC1 Conversion Done Vector Number IVT Address 13 00002Eh Interrupt Bit Locations AIVT Address Flag Enable Priority 00012Eh IFS0<13> IEC0<13> IPC3<6:4> Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12> External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0> External Interrupt 1 20 00003Ch 00013Ch IFS1<4>
PIC24FJ128GA010 FAMILY 7.3 Interrupt Control and Status Registers The PIC24FJ128GA010 family devices implement a total of 29 registers for the interrupt controller: • • • • • • INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC14, and IPC16 INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources.
PIC24FJ128GA010 FAMILY REGISTER 7-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0 (2,3) (2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) IPL2 IPL1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111
PIC24FJ128GA010 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting
PIC24FJ128GA010 FAMILY REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 =
PIC24FJ128GA010 FAMILY REGISTER 7-5: U-0 — bit 15 R/W-0 T2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 — R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF bit 8 R/W-0 OC2IF R/W-0 IC2IF U-0 — R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF R/W-0 INT0IF bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘
PIC24FJ128GA010 FAMILY REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1
PIC24FJ128GA010 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 — — PMPIF — — — OC5IF — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIF: Parallel Master Port Interrupt Flag Stat
PIC24FJ128GA010 FAMILY REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — PMPIF — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IF INT3IF — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit
PIC24FJ128GA010 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has
PIC24FJ128GA010 FAMILY REGISTER 7-10: U-0 — bit 15 R/W-0 T2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 OC2IE R/W-0 IC2IE U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read
PIC24FJ128GA010 FAMILY REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 =
PIC24FJ128GA010 FAMILY REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 — — PMPIE — — — OC5IE — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIE: Parallel Master Port Interrupt Enabl
PIC24FJ128GA010 FAMILY REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IE INT3IE — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1
PIC24FJ128GA010 FAMILY REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request is en
PIC24FJ128GA010 FAMILY REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T
PIC24FJ128GA010 FAMILY REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interru
PIC24FJ128GA010 FAMILY REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ128GA010 FAMILY REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: A/D Conversion Complete Inte
PIC24FJ128GA010 FAMILY REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ128GA010 FAMILY REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interru
PIC24FJ128GA010 FAMILY REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interru
PIC24FJ128GA010 FAMILY REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ128GA010 FAMILY REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Pri
PIC24FJ128GA010 FAMILY REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capt
PIC24FJ128GA010 FAMILY REGISTER 7-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC5IP2 OC5IP1 OC5IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 OC5IP<2:0>: Output Compare Channel 5 Inter
PIC24FJ128GA010 FAMILY REGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: Master I2C2 E
PIC24FJ128GA010 FAMILY REGISTER 7-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT4IP2 IN4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT3IP2 INT3IP1 INT3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External Interrupt 4
PIC24FJ128GA010 FAMILY REGISTER 7-29: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits
PIC24FJ128GA010 FAMILY REGISTER 7-30: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP2:0>: CRC
PIC24FJ128GA010 FAMILY REGISTER 7-31: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 x = Bit is unknown CPUIRQ: Interrupt Request from Inter
PIC24FJ128GA010 FAMILY 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx Control register. The priority level will depend on the specific application and type of interrupt source.
PIC24FJ128GA010 FAMILY 8.0 • On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown OSCILLATOR CONFIGURATION Note: This data sheet summarizes the features of this group of PIC24F devices.
PIC24FJ128GA010 FAMILY 8.1 CPU Clocking Scheme 8.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSC1 and OSC2 pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the programmable clock divider.
PIC24FJ128GA010 FAMILY 8.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers: • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 8-1) is the main control register for the oscillator. It controls clock source switching, and allows the monitoring of clock sources. REGISTER 8-1: The Clock Divider register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator.
PIC24FJ128GA010 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 5 LOCK: PLL Lock Status bit(2) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 Unimplemented: Read as ‘0’ bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bi
PIC24FJ128GA010 FAMILY REGISTER 8-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit a
PIC24FJ128GA010 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 = Maximum frequency
PIC24FJ128GA010 FAMILY 8.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 8.4.1 Primary oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMD Configuration bits.
PIC24FJ128GA010 FAMILY A recommended code sequence for a clock switch includes the following: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSC control bits in the instruction immediately following the unlock sequence.
PIC24FJ128GA010 FAMILY 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 10. PowerSaving Features” (DS39698) in the “PIC24F Family Reference Manual” for more information. The PIC24FJ128GA010 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals.
PIC24FJ128GA010 FAMILY 9.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active.
PIC24FJ128GA010 FAMILY 10.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711) in the “PIC24F Family Reference Manual” for more information. All of the device pins (except VDD, VSS, MCLR and OSC1/CLKI) are shared between the peripherals and the parallel I/O ports.
PIC24FJ128GA010 FAMILY 10.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g.
PIC24FJ128GA010 FAMILY 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ128GA010 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States, even in Sleep mode, when the clocks are disabled.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 110 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 11.0 Note: Figure 11-1 presents a block diagram of the 16-bit timer module. TIMER1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 14. “Timers” (DS39704) in the “PIC24F Family Reference Manual” for more information. To configure Timer1 for operation: 1. 2. 3.
PIC24FJ128GA010 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14
PIC24FJ128GA010 FAMILY 12.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 14. “Timers” (DS39704) in the “PIC24F Family Reference Manual” for more information. The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent, 16-bit timers with selectable operating modes. To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. 2. 3. 4.
PIC24FJ128GA010 FAMILY FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK (T4CK) 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE TGATE TCS Q 1 Set T3IF (T5IF) Q 0 PR3 (PR5) A/D Event Trigger* Equal D CK PR2 (PR4) Comparator MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 Read TMR2 (TMR4) Write TMR2 (TMR4) 16 TMR3HLD (TMR5HLD) 16 Data Bus<15:0> Note: * The 32-bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation.
PIC24FJ128GA010 FAMILY FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON T2CK (T4CK) TCKPS<1:0> 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS TCY 1 Set T2IF (T4IF) 0 Reset Equal Q D Q CK TGATE TMR2 (TMR4) Sync Comparator PR2 (PR4) FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) Sync 1x TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 01 00 TGATE TCY 1 Set T3IF (T5IF) 0 Reset A/D Event Trigger* Equal Q D Q CK TCS TGATE TMR3
PIC24FJ128GA010 FAMILY REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 TCKPS1 R/W-0 R/W-0 U-0 R/W-0 U-0 TCKPS0 T32(1) — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0
PIC24FJ128GA010 FAMILY REGISTER 12-2: R/W-0 TON (1) TyCON: TIMER3 AND TIMER5 CONTROL REGISTER U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 — TGATE(1) TCKPS1(1) TCKPS0(1) U-0 — U-0 R/W-0 U-0 — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 118 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 13.0 INPUT CAPTURE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 15. “Input Capture” (DS39701) in the “PIC24F Family Reference Manual” for more information. The input capture module has multiple operating modes, which are selected via the ICxCON register.
PIC24FJ128GA010 FAMILY 13.
PIC24FJ128GA010 FAMILY 14.0 Note: 14.1 • Dual Compare Match mode generating: - Single Output Pulse mode - Continuous Output Pulse mode • Simple Pulse-Width Modulation mode: - with Fault protection input - without Fault protection input OUTPUT COMPARE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 16. “Output Compare” (DS39706) in the “PIC24F Family Reference Manual” for more information. 14.
PIC24FJ128GA010 FAMILY To generate a single output pulse, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): 1. Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. Calculate time to the rising edge of the output pulse relative to the TMRy start value (0000h). 3.
PIC24FJ128GA010 FAMILY 14.4 EQUATION 14-1: Pulse-Width Modulation Mode The following steps should be taken when configuring the output compare module for PWM operation: 1. 2. 3. 4. 5. 6. PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Set the PWM period by writing to the selected Timer Period register (PRy). Set the PWM duty cycle by writing to the OCxRS register. Write the OCxR register with the initial duty cycle.
PIC24FJ128GA010 FAMILY EXAMPLE 14-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) 1. Find the Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2/FOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value) 19.2 s = (PR2 + 1) • 62.5 ns • 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.
PIC24FJ128GA010 FAMILY REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 — — U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 — OCFLT(1) OCTSEL(1) OCM2 OCM1 OCM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bi
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 126 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 15.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 23. “Serial Peripheral Interface (SPI)” (DS39699) in the “PIC24F Family Reference Manual” for more information. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices.
PIC24FJ128GA010 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation: To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1.
PIC24FJ128GA010 FAMILY FIGURE 15-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE) SCKx 1:1 to 1:8 Secondary Prescaler SSx/FSYNCx Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPIxCON1<1:0> Shift Control SDOx SPIxCON1<4:2> Enable Master Clock bit 0 SDIx FCY SPIxSR Transfer Transfer 8-Level FIFO Receive Buffer 8-Level FIFO Transmit Buffer SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R-0 R-0 R-0 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SP
PIC24FJ128GA010 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
PIC24FJ128GA010 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 — bit 15 U-0 — U-0 — R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 SSEN bit 7 R/W-0 CKP R/W-0 MSTEN R/W-0 SPRE2 R/W-0 SPRE1 R/W-0 SPRE0 R/W-0 PPRE1 R/W-0 PPRE0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 bit 1-0 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cl
PIC24FJ128GA010 FAMILY REGISTER 15-3: R/W-0 FRMEN bit 15 SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 SPIFSD R/W-0 SPIFPOL U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 14 bit 13 bit 12-2 bit 1 bit 0 U-0 — U-0 — bit 8 U-0 — bit 15 U-0 — W = Writable bit ‘1’ = Bit is set U-0 — R/W-0 SPIFE R/W-0 SPIBEN bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled
PIC24FJ128GA010 FAMILY FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave) SDIx SDOx Serial Receive Buffer (SPIxRXB) Serial Receive Buffer (SPIxRXB) SDOx SDIx Shift Register (SPIxSR) LSb MSb MSb Serial Transmit Buffer (SPIxTXB) LSb Serial Transmit Buffer (SPIxTXB) SCKx SPIx Buffer (SPIxBUF) Shift Register (SPIxSR) Serial Clock SCKx SPIx Buffer (SPIxBUF) SSx (SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0) (MSTEN (SPIxCON1<5> = 1
PIC24FJ128GA010 FAMILY FIGURE 15-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Slave, Frame Slave) SDIx SDOx SDOx SDIx SCKx SSx FIGURE 15-6: Serial Clock Frame Sync Pulse SCKx SSx SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PROCESSOR 2 PIC24F SPI Master, Frame Slave) SDOx SDIx SDIx SDOx SCKx SSx FIGURE 15-7: Serial Clock Frame Sync Pulse SCKx SSx SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Slave, Frame Slave) SDOx SDIx SDIx SDOx SCKx SS
PIC24FJ128GA010 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FCY FSCK = Primary Prescaler * Secondary Prescaler Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
PIC24FJ128GA010 FAMILY 16.0 Note: INTER-INTEGRATED CIRCUIT (I2C™) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 24. “InterIntegrated Circuit™ (I2C™)” (DS39702) in the “PIC24F Family Reference Manual” for more information. The Inter-Integrated Circuit (I2C) module is a serial interface useful for communicating with other peripheral or microcontroller devices.
PIC24FJ128GA010 FAMILY FIGURE 16-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS39747F-page 138 2005-2012 Microchip Te
PIC24FJ128GA010 FAMILY 16.2 Setting Baud Rate When Operating as a Bus Master 16.3 The I2CxMSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond, whether the corresponding address bit value is a ‘0’ or ‘1’. For example, when I2CxMSK is set to ‘00100000’, the slave module will detect both addresses, ‘0000000’ and ‘00100000’.
PIC24FJ128GA010 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = B
PIC24FJ128GA010 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (When operating as an I2C master; applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (When operating as an I2C master; applicable during master receive.
PIC24FJ128GA010 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HSC R/C-0, HSC R-0, HSC IWCOL I2COV D/A R/C-0, HSC R/C-0, HSC P S R-0, HSC R-0, HSC R-0, HSC R/W RBF TBF bit 7 bit 0 HS = Hardware Settable bit Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = B
PIC24FJ128GA010 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected.
PIC24FJ128GA010 FAMILY REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 A
PIC24FJ128GA010 FAMILY 17.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” for more information. The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24F device family.
PIC24FJ128GA010 FAMILY 17.1 UARTx Baud Rate Generator (BRG) The UARTx module includes a dedicated, 16-bit Baud Rate Generator. The UBRGx register controls the period of a free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 17-1: Note 1: FCY 16 • (UBRGx + 1) UBRGx = FCY –1 16 • Baud Rate Based on FCY = FOSC/2; Doze mode and PLL are disabled.
PIC24FJ128GA010 FAMILY 17.2 1. 2. 3. 4. 5. 6. Set up the UARTx: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UBRGx register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UARTx. Set the UTXEN bit (causes a transmit interrupt). Write data byte to lower byte of UTXxREG word.
PIC24FJ128GA010 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN — USIDL IREN(1) RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit
PIC24FJ128GA010 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note
PIC24FJ128GA010 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1 UTXISEL1 TXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clea
PIC24FJ128GA010 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 152 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 18.0 Note: PARALLEL MASTER PORT (PMP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 13. “Parallel Master Port (PMP)” (DS39713) in the “PIC24F Family Reference Manual” for more information.
PIC24FJ128GA010 FAMILY REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN bit 15 bit 8 R/W-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Paralle
PIC24FJ128GA010 FAMILY REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable is active-high (PMBE) 0 = Byte enable is active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe is active-high (PMWR) 0 = Write strobe is active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe is active-high (PMENB) 0 = Enable strobe is active-low (PMENB) bit 0 RDSP:
PIC24FJ128GA010 FAMILY REGISTER 18-2: PMMODE: PARALLEL PORT MODE REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB1(1) WAITB0(1) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(1) WAITE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
PIC24FJ128GA010 FAMILY REGISTER 18-3: PMADDR: PARALLEL PORT ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 CS1 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CS2: Chip Select 2 bit 1 = Chi
PIC24FJ128GA010 FAMILY REGISTER 18-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1
PIC24FJ128GA010 FAMILY REGISTER 18-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC Second
PIC24FJ128GA010 FAMILY FIGURE 18-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Master PIC24F Slave PMD<7:0> FIGURE 18-3: PMD<7:0> PMCS PMCS PMRD PMRD PMWR PMWR Address Bus Data Bus Control Lines ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PIC24F Slave PMA<1:0> PMA<1:0> PMD<7:0> PMD<7:0> Write Address Decode Read Address Decode PMDOUT1L (0) PMDIN1L (0) PMCS PMCS PMDOUT1H (1) PMDIN1H (1) PMRD PMRD PMDOUT2L (2) PMDIN2L (2) PMWR PMDOUT2H (3) PMDIN2H (3) PMWR Address Bus Data Bus Cont
PIC24FJ128GA010 FAMILY FIGURE 18-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PMA<13:8> PIC24F PMD<7:0> PMA<7:0> PMCS1 PMCS2 Address Bus PMALL Multiplexed Data and Address Bus PMRD Control Lines PMWR FIGURE 18-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PMD<7:0> PMA<13:8> PIC24F PMCS1 PMCS2 PMALL PMALH Multiplexed Data and Address Bus PMRD Control Lines PMWR FIGURE 18-7: EXAMPLE OF
PIC24FJ128GA010 FAMILY FIGURE 18-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F Parallel Peripheral PMD<7:0> PMALL AD<7:0> ALE PMCS1 CS Address Bus PMRD RD Data Bus PMWR WR Control Lines FIGURE 18-10: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) PIC24F PMA Parallel EEPROM A PMD<7:0> D<7:0> PMCS1 CE PMRD OE PMWR WR FIGURE 18-11: Address Bus Data Bus Control Lines PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA) PIC24F P
PIC24FJ128GA010 FAMILY 19.0 Note: • • • • • • • • Calendar: Weekday, Date, Month and Year Alarm Configurable Year Range: 2000 to 2099 Leap Year Correction BCD Format for Compact Firmware Optimized for Low-Power Operation User Calibration with Auto-Adjust Calibration Range: ±2.64 Seconds Error per Month • Requirements: External 32.
PIC24FJ128GA010 FAMILY 19.1 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 19.1.1 By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR<1:0>, decrements by one until it reaches ‘00’. Once it reaches ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed.
PIC24FJ128GA010 FAMILY 19.1.
PIC24FJ128GA010 FAMILY RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) REGISTER 19-1: bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute ...
PIC24FJ128GA010 FAMILY REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 AL
PIC24FJ128GA010 FAMILY 19.1.
PIC24FJ128GA010 FAMILY REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDA
PIC24FJ128GA010 FAMILY 19.1.
PIC24FJ128GA010 FAMILY REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unk
PIC24FJ128GA010 FAMILY 19.2 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute.
PIC24FJ128GA010 FAMILY FIGURE 19-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK<3:0>) Day of the Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s m s s m m s s 0100 – Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week d 1000 – Every month 1001 – Every year(1) Note 1: m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Annually, except when conf
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 174 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 20.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR 20.2 The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the CRCXOR (X<15:1>) bits and the CRCCON (PLEN<3:0>) bits, respectively. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 30.
PIC24FJ128GA010 FAMILY CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1 FIGURE 20-2: XOR D Q D Q D Q D Q D Q SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 p_clk p_clk p_clk p_clk p_clk CRC Read Bus CRC Write Bus 20.3 20.3.1 User Interface DATA INTERFACE To start serial shifting, a ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8-deep when PLEN<3:0> (CRCCON<3:0>) > 7 and 16-deep otherwise.
PIC24FJ128GA010 FAMILY REGISTER 20-1: CRCCON: CRC CONTROL REGISTER U-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0 R-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CR
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 178 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 21.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 17. “10-Bit A/D Converter” (DS39705) in the “PIC24F Family Reference Manual” for more information. A block diagram of the A/D Converter is shown in Figure 21-1. To perform an A/D conversion: 1.
PIC24FJ128GA010 FAMILY Figure 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VR Select AVDD 16 VR+ VR- Comparator VREF- VINH VINL AN0 AN1 VRS/H VINH 10-Bit SAR AN4 MUX A AN2 AN3 AN5 VINL ADC1BUF0: ADC1BUFF AN7 AN8 AD1CON1 AD1CON2 AD1CON3 AD1CHS AN12 MUX B AN9 AN11 Conversion Logic Data Formatting AN6 AN10 VR+ DAC VINH AD1PCFG AD1CSSL VINL AN13 AN14 AN15 DS39747F-page 180 Sample Control Control Logic Conversion Control Input MUX Control
PIC24FJ128GA010 FAMILY REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/C-0, HCS SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkn
PIC24FJ128GA010 FAMILY REGISTER 21-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 r — CSCNA — — bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Voltage Reference Conf
PIC24FJ128GA010 FAMILY REGISTER 21-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source bit 1 = A/D interna
PIC24FJ128GA010 FAMILY REGISTER 21-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for MUX
PIC24FJ128GA010 FAMILY REGISTER 21-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PCF
PIC24FJ128GA010 FAMILY A/D CONVERSION CLOCK PERIOD(1) EQUATION 21-1: TAD = TCY (ADCS + 1) TAD –1 ADCS = TCY Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled. FIGURE 21-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA RIC 250 VT = 0.6V ANx CPIN 6-11 pF (Typical) VT = 0.6V Sampling Switch RSS 5 k(Typical) RSS ILEAKAGE 500 nA CHOLD = DAC Capacitance = 4.
PIC24FJ128GA010 FAMILY FIGURE 21-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 188 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 22.0 COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 19. “Comparator Module” (DS39710) in the “PIC24F Family Reference Manual” for more information. FIGURE 22-1: The analog comparator module contains two comparators that can be configured in a variety of ways.
PIC24FJ128GA010 FAMILY REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER R/W-0 U-0 R/C-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN bit 15 bit 8 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL
PIC24FJ128GA010 FAMILY REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED) bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output is inverted 0 = C2 output is not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output is inverted 0 = C1 output is not inverted bit 3 C2NEG: Comparator 2 Negative Input Configure bit 1 = C2IN+ is connected to VIN0 = C2IN- is connected to VINSee Figure 22-1 for the Comparator modes.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 192 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 23.0 Note: 23.1 voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. COMPARATOR VOLTAGE REFERENCE This data sheet summarizes features of PIC24F group of devices and is not intended to be a comprehensive reference source. Refer to Section 20.
PIC24FJ128GA010 FAMILY REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Compara
PIC24FJ128GA010 FAMILY 24.0 Note: SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 32. “High-Level Device Integration” (DS39719) in the “PIC24F Family Reference Manual” for more information. PIC24FJ128GA010 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components.
PIC24FJ128GA010 FAMILY REGISTER 24-1: FLASH CONFIGURATION WORD 1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 r-x r bit 16 R/PO-1 (1) JTAGEN R/PO-1 R/PO-1 R/PO-1 r-1 U-1 R/PO-1 GCP GWRP DEBUG r — ICS bit 15 bit 8 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: x = Bit is unknown r = Reserved R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘0’ -
PIC24FJ128GA010 FAMILY REGISTER 24-1: bit 3-0 Note 1: FLASH CONFIGURATION WORD 1 (CONTINUED) WDTPS<3:0>: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial Programming™ (ICSP™).
PIC24FJ128GA010 FAMILY REGISTER 24-2: FLASH CONFIGURATION WORD 2 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 U-1 U-1 U-1 U-1 R/PO-1 R/PO-1 R/PO-1 IESO — — — — FNOSC2 FNOSC1 FNOSC0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 U-1 U-1 U-1 R/PO-1 R/PO-1 FCKSM1 FCKSM0 OSCIOFCN — — — POSCMD1 POSCMD0 bit 7 bit 0 Legend: x = Bit is unknown R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed U = Unimplemented bit, r
PIC24FJ128GA010 FAMILY REGISTER 24-3: DEVID: DEVICE ID REGISTER U U U U U U U U — — — — — — — — bit 23 bit 16 U U R R R R R R — — FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 bit 15 bit 8 R R R R R R R R FAMID1 FAMID0 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: x = Bit is unknown R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘1’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-14 Unimplemented: Read as
PIC24FJ128GA010 FAMILY REGISTER 24-4: DEVREV: DEVICE REVISION REGISTER U U U U U U U U — — — — — — — — bit 23 bit 16 R-0 R-0 R-1 R-1 U U U R r r r r — — — MAJRV2 bit 15 bit 8 R R U U U R R R MAJRV1 MAJRV0 — — — DOT2 DOT1 DOT0 bit 7 bit 0 Legend: x = Bit is unknown R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘1’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘0’ bit 15-12 Res
PIC24FJ128GA010 FAMILY 24.2 On-Chip Voltage Regulator All of the PIC24FJ128GA010 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ128GA010 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin.
PIC24FJ128GA010 FAMILY 24.3 Watchdog Timer (WDT) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 9. “Watchdog Timer (WDT)” (DS39697) in the “PIC24F Family Reference Manual” for more information. For PIC24FJ128GA010 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 32 kHz.
PIC24FJ128GA010 FAMILY 24.4 Note: JTAG Interface This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 33. “Programming and Diagnostics” (DS39716) in the “PIC24F Family Reference Manual” for more information. PIC24FJ128GA010 family devices implement a JTAG interface, which supports boundary scan device testing as well as In-Circuit Serial Programming™ (ICSP™). Refer to the Microchip web site (www.microchip.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 204 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 25.0 INSTRUCTION SET SUMMARY The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24FJ128GA010 FAMILY TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...
PIC24FJ128GA010 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C,
PIC24FJ128GA010 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax # of Words Description # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
PIC24FJ128GA010 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 W
PIC24FJ128GA010 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 No
PIC24FJ128GA010 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 212 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 26.
PIC24FJ128GA010 FAMILY 26.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC24FJ128GA010 FAMILY 26.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24FJ128GA010 FAMILY 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC24FJ128GA010 FAMILY 27.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ128GA010 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ128GA010 are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24FJ128GA010 FAMILY 27.1 DC Characteristics TABLE 27-1: OPERATING MIPS vs. VOLTAGE Max MIPS VDD Range (in Volts) Temp Range (in °C) PIC24FJ128GA010 Family 2.0-3.
PIC24FJ128GA010 FAMILY TABLE 27-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC20 1.6 4.0 mA -40°C DC20a 1.6 4.0 mA +25°C DC20b 1.6 4.0 mA +85°C DC20d 1.6 4.0 mA -40°C DC20e 1.6 4.0 mA +25°C DC20f 1.6 4.0 mA +85°C DC23 6.0 12 mA -40°C DC23a 6.
PIC24FJ128GA010 FAMILY TABLE 27-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE): Core Off, Clock On Base Current(2) DC40 0.7 2 mA -40°C DC40a 0.7 2 mA +25°C DC40b 0.7 2 mA +85°C DC40d 0.7 2 mA -40°C DC40e 0.7 2 mA +25°C DC40f 0.7 2 mA +85°C DC43 2.
PIC24FJ128GA010 FAMILY TABLE 27-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD)(2) DC60 3 25 A -40°C DC60a 3 45 A +25°C DC60b 100 600 A +85°C DC60f 20 40 A -40°C DC60g 27 60 A +25°C DC60h 120 600 A +85°C 2.0V(3) Base Power-Down Current(5) 3.
PIC24FJ128GA010 FAMILY TABLE 27-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Param No. Sym VIL DI10 Characteristic Min Typ(1) Max Units VSS — 0.2 VDD V Input Low Voltage(4) I/O Pins with ST Buffer DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (XT mode) VSS — 0.
PIC24FJ128GA010 FAMILY TABLE 27-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL Characteristic I/O Ports DO16 OSC2/CLKO DO20 DO26 Note 1: Min Typ(1) Max Units — — 0.4 V IOL = 8.5 mA, VDD = 3.6V — — 0.4 V IOL = 6.0 mA, VDD = 2.0V — — 0.4 V IOL = 8.5 mA, VDD = 3.6V — — 0.4 V IOL = 6.0 mA, VDD = 2.0V Conditions Output Low Voltage DO10 VOH Standard Operating Conditions: 2.0V to 3.
PIC24FJ128GA010 FAMILY TABLE 27-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Param. Symbol IICL Characteristic Min. Typ(1) Max.
PIC24FJ128GA010 FAMILY TABLE 27-11: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ(1) Max Units Conditions Program Flash Memory D130 EP Cell Endurance 100 1K — E/W D131 VPR VDD for Read VMIN — 3.6 V 2.25 — 3.
PIC24FJ128GA010 FAMILY TABLE 27-13: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No.
PIC24FJ128GA010 FAMILY 27.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ128GA010 AC characteristics and timing parameters. TABLE 27-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Operating voltage VDD range as described in Section 27.1 “DC Characteristics”.
PIC24FJ128GA010 FAMILY FIGURE 27-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OS30 OS30 Q1 Q3 Q2 OSC1 OS20 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 27-17: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic FOSC External CLKI Frequency (external clocks allowed only in EC mode) Oscillator Frequency Standard Operating Conditions: 2.0V to 3.
PIC24FJ128GA010 FAMILY TABLE 27-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
PIC24FJ128GA010 FAMILY FIGURE 27-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 27-2 for load conditions. TABLE 27-21: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No.
PIC24FJ128GA010 FAMILY TABLE 27-22: A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.0 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.
PIC24FJ128GA010 FAMILY TABLE 27-23: A/D CONVERSION TIMING REQUIREMENTS(1) AC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 2.0V to 3.
PIC24FJ128GA010 FAMILY 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC24FJ128 GA006-I/ PT e3 1110017 80-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN * Note: Example PIC24FJ128GA 010-I/PT e3 1110017 100-Lead TQFP (14x14x1 mm) Legend: XX...
PIC24FJ128GA010 FAMILY 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN DS39747F-page 234 Example PIC24FJ128 GA010-I/MR e3 1150017 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 28.2 Package Details The following sections give the technical details of the packages.
PIC24FJ128GA010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39747F-page 236 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c β φ A2 A1 L1 L Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 80 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.
PIC24FJ128GA010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39747F-page 238 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY 100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 Units Dimension Limits Number of Leads A2 L1 MILLIMETERS MIN N NOM MAX 100 Lead Pitch e Overall Height A – 0.40 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.
PIC24FJ128GA010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39747F-page 240 2005-2012 Microchip Technology Inc.
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PIC24FJ128GA010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39747F-page 242 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39747F-page 244 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 246 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY APPENDIX A: REVISION HISTORY Revision A (September 2005) Original data sheet for PIC24FJ128GA010 family devices. Revision B (March 2006) Update of electrical specifications. Revision C (June 2006) Update of electrical specifications. Revision D (September 2007) Minor changes in the overall data sheet Revision E (October 2009) Updated to remove Preliminary status. Revision F (January 2012) Added Section 2.0 “Guidelines for Getting Started with 16-bit Microcontrollers”.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 248 2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY INDEX A C A/D Conversion Timing Requirements............................. 232 Module Specifications ............................................... 231 AC Characteristics .......................................................... 227 Load Conditions ........................................................ 227 Temperature and Voltage Specifications .................. 227 Alternate Interrupt Vector Table (AIVT) .............................. 63 Arithmetic Logic Unit (ALU).............
PIC24FJ128GA010 FAMILY DC Characteristics ............................................................ 218 Comparator Voltage Reference Specifications.................................................... 226 I/O Pin Input Specifications ............................... 222, 224 I/O Pin Output Specifications .................................... 223 Idle Current (IIDLE) .................................................... 220 Operating Current (IDD).............................................
PIC24FJ128GA010 FAMILY P Packaging ......................................................................... 233 Details ....................................................................... 235 Marking ..................................................................... 233 Parallel Master Port (PMP) ............................................... 153 PIC24FJ128GA010 Family Pinout Descriptions ..................................................... 11 Pin Diagrams .........................................
PIC24FJ128GA010 FAMILY OSCTUN (FRC Oscillator Tune) ............................... 102 PADCFG1 (Pad Configuration Control) .................... 166 PMADDR (Parallel Port Address) ............................. 157 PMAEN (Parallel Port Enable) .................................. 157 PMCON (Parallel Port Control) ................................. 154 PMMODE (Parallel Port Mode) ................................. 156 PMSTAT (Parallel Port Status) .................................
PIC24FJ128GA010 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24FJ128GA010 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC24FJ128GA010 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 128 GA0 10 T - I / PT - XXX Examples: a) Microchip Trademark Architecture b) Flash Memory Family Program Memory Size (KB) Product Group PIC24FJ128GA008-I/PT 301: General purpose PIC24F, 96 Kbyte program memory, 80-pin, Industrial temp., TQFP package, QTP pattern #301.
PIC24FJ128GA010 FAMILY NOTES: DS39747F-page 256 2005-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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