Information

 2009-2011 Microchip Technology Inc. DS80471B-page 9
PIC24FJ128GA010 FAMILY
19. Module: UART
The timing for transmitting a Sync Break has
changed for this revision of silicon. The Sync
Break is transmitted as soon as the UTXBRK bit is
set. A dummy write to UxTXREG is still required
and must be performed before the Sync Break has
finished transmitting. Otherwise, the UxTX may be
held in the active state until the write has occurred.
Work around
Set the UTXBRK bit when a Sync Break is
required and perform a dummy write to UxTXREG
immediately following. This sequence will avoid
holding the UxTX pin in the active state.
Affected Silicon Revisions
20. Module: UART
When the UART is in High-Speed mode, BRGH
(UxMODE<3>) is set, some optimal UxBRG
values can cause reception to fail.
Work around
Test UxBRG values in the application to find a
UxBRG value that works consistently for more
high-speed applications. The user should verify
that the UxBRG baud rate error does not exceed
the application limits.
Affected Silicon Revisions
21. Module: UART
The UTXISEL0 bit (UxSTA<13>) always reads as
zero, regardless of the value written to it. The bit can
be written to either a ‘0’ or ‘1’, but will always read
zero. This will affect read-modify-write operations,
such as bit-wise or shift operations. Using a
read-modify-write instruction on the UxSTA register
will always write the UTXISEL0 bit to zero.
Work around
If a UTXISEL0 value of ‘1’ is needed, avoid using
read-modify-write instructions on the UxSTA
register. Copy the UxSTA register to a temporary
variable and set UxSTA<13> prior to performing
read-modify-write operations. Copy the new value
back to the UxSTA register.
Affected Silicon Revisions
22. Module: UART
When UTXISEL<1:0> = 10, a UART interrupt flag
should be set after one byte from the FIFO is
transferred to the Transmit Shift Register (TSR).
Instead, the interrupt flag may be set only after all
bytes are transferred from the FIFO and the FIFO
is empty. This behavior is similar to the
UTXISEL<1:0> = 00 mode.
Work around
None.
Affected Silicon Revisions
23. Module: UART (Hardware Flow Control)
UART1 and UART2 hardware flow control options
are not available for the 64-pin variants of the
PIC24F128GA010 product family. As a result, the
UxCTS
and UxRTS pins are not available and the
UEN<1:0> control bits are read as ‘0’ (unimple-
mented). UART2 hardware flow control is not
available for the 80-pin PIC24F128GA010 family
variants. Associated pins and bits are not available
for these devices.
Work around
None.
Affected Silicon Revisions
24. Module: UART
When the UART is in High-Speed mode
(BRGH = 1), the auto-baud sequence can
calculate the baud rate as if it were in Low-Speed
mode.
Work around
The calculated baud rate can be modified by the
following equation:
The user should verify that the baud rate error does
not exceed application limits.
Affected Silicon Revisions
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
X
A2 A3 A4 C1 C2
X
A2 A3 A4 C1 C2
XXX
New BRG Value = (Auto-Baud BRG + 1) * 4 • 1
A2 A3 A4 C1
C2
XXX