Information

PIC24FJ128GA010 FAMILY
DS80471B-page 8  2009-2011 Microchip Technology Inc.
14. Module: PMP (Master Mode)
With the PMP in Master mode (MODE<1:0> = 11
or 10) with the increment/decrement feature
enabled (INCM<1:0> = 01 or 10), the address
may not automatically change when the PMDINx
register is read. This issue may occur when
multiple back-to-back reads are performed.
Work around
The PMP address will be generated correctly if a
minimum of one instruction cycle delay is inserted
between the back-to-back read operations of the
PMDINx register. A NOP instruction, or any other
instruction, is adequate.
Affected Silicon Revisions
15. Module: RTCC
An RTCC increment may be missed if an RTCC
update and an RTCC increment occur at the same
time, and updates are disallowed (RTCWREN = 0).
In this condition, the RTCC is not updated since the
RTCWREN bit is clear.
Work around
Prior to writing to the RTCVAL registers, verify that
the RTCSYNC bit is clear and the RTCWREN bit
is set. This ensures that the RTCC will be updated
and the update will not occur during an RTCC
increment.
Affected Silicon Revisions
16. Module: RTCC
The RTCC automatic calibration, stored in the
CAL<7:0> bits, is intended to be applied every
minute on the minute boundary. The calibration is
applied after the first minute but may not occur on
subsequent minute intervals.
Work around
Read and rewrite the SECONDS
(RTCPTR<1:0> = 00) value after each minute.
This reinitializes the calibration circuit and allows
the calibration to be applied to the next minute
increment.
Affected Silicon Revisions
17. Module: I
2
C (Slave Mode)
In I
2
C Slave mode, the I
2
C peripheral may not
Acknowledge a write operation (R/W = 0) after a
Restart has been received. This sequence is
typically used to perform a slave transmit opera-
tion in 10-Bit Addressing mode (A10M = 1).
Attempting to perform a write operation after a
Restart may cause the peripheral to generate a
NACK and end the operation unexpectedly.
Work around
To perform an I
2
C slave transmit, refer to
Figure 24-27 from Section 24. “Inter-Integrated
Circuit™ (I
2
C™)” in the “PIC24F Family Reference
Manual” (DS39702).
Affected Silicon Revisions
18. Module: I
2
C
I
2
C Receive mode should be enabled (i.e., RCEN
bit should be set) only when the system is Idle (i.e.,
when ACKEN, RCEN, PEN, RSEN and SEN all
equal zero). It should not be possible to set the
RCEN bit when the system is not Idle; however,
the RCEN bit can be set under this circumstance.
Work around
Wait for the system to become Idle before setting
the RCEN bit. Verify that the following bits are
clear:
ACKEN, RCEN, PEN, RSEN and SEN.
Affected Silicon Revisions
A2 A3 A4 C1 C2
X
A2 A3 A4 C1 C2
X
A2 A3 A4 C1 C2
X
A2 A3 A4 C1 C2
X
A2 A3 A4 C1 C2
X