Information

 2009-2011 Microchip Technology Inc. DS80471B-page 5
PIC24FJ128GA010 FAMILY
Silicon Errata Issues
1. Module: Core
With Doze mode enabled, DOZEN (CLKDIV<11>)
set and the CPU Peripheral Clock Ratio Select bits
(CLKDIV<14:12>) configured to any value except
‘000’, writes to SFR locations can not be
performed.
Work around
Disable Doze mode or select 1:1 CPU peripheral
clock ratio before modifying stated SFR locations,
or avoid writing stated locations while Doze mode
is enabled and a CPU peripheral clock ratio other
than 1:1 is selected. Configure the device prior to
entering Doze mode and use the mode only to
monitor applications activity.
Affected Silicon Revisions
2. Module: I
2
C™
Writing to I2CxTRN during a Start bit transmission
generates a write collision, indicated by the
IWCOL (I2CxSTAT<7>) bit being set. In this state,
additional writes to the I2CxTRN register should
be blocked. However, in this condition, the
I2CxTRN register can be written, although
transmissions will not occur until the IWCOL bit is
cleared in software.
Work around
After each write to the I2CxTRN register, read the
IWCOL bit to ensure a collision has not occurred.
If the IWCOL bit is set, it must be cleared in
software and I2CxTRN must be rewritten.
Affected Silicon Revisions
3. Module: UART
With the parity option enabled, a parity error,
indicated with the PERR bit (UxSTA<3>) being set,
may occur if the Baud Rate Generator contains an
odd value. This affects both even and odd parity
options.
Work around
Load the Baud Rate Generator register, UxBRG,
with an even value or disable the peripheral’s par-
ity option by loading either ‘00’ or ‘11’ into the
Parity and Data Selection bits, PDSEL<1:0>
(UxMODE<2:1>).
Affected Silicon Revisions
4. Module: Resets
After an oscillator has stopped, with the Fail-Safe
Clock Monitor enabled and the FCKSM<1:0> Con-
figuration bits (Flash Configuration Word 2<7:6>)
programmed to ‘00’, the system clock source is
forced to FRC. After which, the system clock source
may not be changed in software by modifying the
New Oscillator Selection bits, NOSC<2:0>
(OSCCON<10:8>), unless a device Reset occurs.
Work around
Upon detecting an oscillator failure, determined by
reading the Clock Fail Detect bit, CF
(OSCCON<3>), as set, execute a RESET instruc-
tion prior to selecting a new system clock source
using the NOSC bits.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (C2).
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
X
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
X