Information

 2009-2011 Microchip Technology Inc. DS80471B-page 3
PIC24FJ128GA010 FAMILY
SPI Slave mode 30. Module in Slave mode may ignore SSx pin
and receive data anyway.
XXX
Oscillator Two-Speed
Start-up
31. Two-Speed Start-up failure when IESO is
enabled.
XXX
Core Reset 32. Unimplemented CLKDIV bits reset to ‘1’. XXX
Core Traps 33. Clock failure trap does not vector as
expected.
XXX
Core Resets 34. BOR and POR flags are both set on BOR. X X X
I/O Ports — 35. OSCO/CLKO/RC15 driven immediately
following POR.
XXX
I
2
C Slave mode 36. D/A bit fails to update in Slave mode
transmissions.
XXX
UART Auto-Baud 37. Double receive interrupt with auto-baud
reception.
XXX
UART Auto-Baud 38. Auto-baud calculation errors causing
transmit or receive failures.
XXX
UART — 39. Erroneous sampling and framing errors
when using two Stop bits.
XXXXX
SPI — 40. DISSCK does not disable the SPIx clock. X X X
Output
Compare
PWM mode 41. Single missed compare events under
certain conditions.
XXX
CRC — 42. Improper VWORD Reset on FIFO overflow. X X X
UART IrDA
®
43. IR baud clock only available during transmit. X X
I
2
C—44. Issues with write operations on I2CxSTAT. X
I
2
C—45. ACKSTAT prematurely cleared in Slave
mode.
XXX
RTCC — 46. Write errors to ALCFGRPT register. X X X
Core Instruction
Set
47. Loop count errors with REPEAT instruction
and R-A-W stalls.
XXX
Memory PSV 48. False address error traps at lower
boundary of PSV space.
XXX
I/O PORTB 49. RB5 as an open-drain output stays in
high-impedance state.
XXX
RTCC Alarm 50. Decrement of alarm repeat counter under
certain conditions.
XXXXX
UART UERIF
Interrupt
51. No UERIF flag with multiple errors. X X X
UART FIFO Error
Flags
52. PERR and FERR not correctly set for all
bytes in receive FIFO.
XXX
UART — 53. Does not transmit if TxREG is preloaded. X X X
I
2
CMaster mode54. Module may respond to its own master
transmission as a slave under certain
conditions.
XXX
I
2
C Slave mode 55. Failure to respond correctly to some
reserved addresses in 10-bit mode.
XXX
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A2 A3 A4 C1 C2
Note 1: Only those issues indicated in the last column apply to the current silicon revision.