Information

PIC24FJ128GA010 FAMILY
DS80471B-page 2  2009-2011 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A2 A3 A4 C1 C2
Core — 1. SFR write issues in Doze mode. X X X
I
2
C™ — 2. Failure to lock out writes to I2CxTRN. X
UART — 3. Parity failure with odd values in BRG. X X X
Resets — 4. FSCM clock switch issue. X
Timers — 5. Special Event Trigger failure (Timer2/3). X
SPI Enhanced
mode
6. Enhanced Buffer modes are unavailable. X X X
JTAG Programming 7. JTAG device programming not compatible
with third party solutions.
XXX
A/D — 8. High gain error. X X X
I
2
C—9. Failure to detect bus collision in Stop or
Restart sequences.
X
UART — 10. Erroneous FIFO buffer overflow flag. X
SPI Master mode 11. Master mode reception errors at fast bit
rates.
XXX
CPU — 12. Skipped DISI instruction under certain
circumstances.
X
PMP — 13 PMRD
signal absent in Master mode under
certain conditions.
XXX
PMP Master mode 14. Address increment/decrement failure on
back-to-back reads in Master mode.
X
RTCC — 15. Missed increments on simultaneous
register update.
X
RTCC — 16. Calibration not applied at every interval. X
I
2
C Slave mode 17. Failure to Acknowledge write operation in
Slave mode.
X
I
2
C—18. Receive mode can be enabled outside of
Idle state.
X
UART — 19. Change in Sync Break timing. X X X
UART — 20. Reception failures in High-Speed mode. X X X
UART — 21. UTXISEL0 bit always reads as ‘0’. X
UART — 22. UTXSEL mode ‘10’ behaves as mode ‘00’. X
UART HW Flow
Control
23. Hardware flow control unavailable for some
devices and some UARTs.
XXX
UART — 24. Erroneous baud rate calculations in
High-Speed mode.
XXX
UART Auto-Baud 25. Insertion of spurious data with auto-baud
reception.
XXX
Interrupts Traps 26. Failure to exit Doze mode on certain traps. X X X
Output
Compare
— 27. Single glitch on initialization under certain
conditions.
XXX
A/D INT0 Trigger 28. Device may not wake when convert on
INT0 trigger is selected.
XXX
SPI Framed
modes
29. Frame Sync unavailable in Master mode
under certain conditions.
XXX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.