Information

PIC24FJ128GA010 FAMILY
DS80471B-page 18  2009-2011 Microchip Technology Inc.
60. Module: SPI (Framed SPIx Modes)
Framed SPIx modes, as described in the device
data sheet, are not supported. When using the
module, verify the FRMEN bit (SPIxCON2<15>) is
cleared.
All other SPIx modes function as described.
Work around
None.
Affected Silicon Revisions
61. Module: SPI (Enhanced Mode)
SPIx operating in Enhanced Buffer mode
(SPIBEN = 1) may set the interrupt flag, SPIxIF,
before the last bit has been transmitted from the
Shift register. This issue only affects one of the
eight interrupt modes, SISEL<2:0> = 101, which
generates an interrupt when the last bit has shifted
out of the Shift register, indicating the transfer is
complete. All other interrupt modes in Enhanced
Buffer mode work as described in the device data
sheet.
Work around
Multiple work arounds are available. Select
another Buffer Interrupt mode using the
SISEL<2:0> bits in the SPIxSTAT register. A com-
parable mode is to generate an interrupt when the
FIFO is empty (SISEL<2:0> = 110). Another
option is to monitor the SRMPT bit (SPIxSTAT<7>)
to determine when the Shift register is empty.
Affected Silicon Revisions
62. Module: Core (Code Protection)
When general segment code protection has been
enabled (GCP Configuration bit is programmed),
applications are unable to write to the first
512 bytes of the program memory space (0000h
through 0200h). In applications that may require
the interrupt vectors to be changed during run
time, such as bootloaders, modifications to the
interrupt vector tables will not be possible.
Work around
Create two new interrupt vector tables, one each
for the IVT and AIVT, in an area of program space
beyond the affected region. Map the addresses in
the old vector tables to the new tables. These new
tables can then be modified as needed to the
actual addresses of the ISRs.
Affected Silicon Revisions
63. Module: UART (Transmit Interrupt)
When using UTXISEL<1:0> = 01 (interrupt when
the last character is shifted out of the Transmit
Shift register) and the final character is being
shifted out through the Transmit Shift Register
(TSR), the TX interrupt may occur before the final
bit is shifted out.
Work around
If it is critical that the interrupt processing occurs
only when all transmit operations are complete,
after which the following work around can be
implemented:
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift register empty bit, as shown in
Example 2.
Affected Silicon Revisions
EXAMPLE 2: DELAYING THE ISR BY POLLING THE TRMT BIT
A2 A3 A4 C1 C2
X
X
A2 A3 A4 C1
C2
X
X
A2 A3 A4 C1 C2
X
A2 A3 A4 C1 C2
X
X
// in UART2 initialization code
...
U2STAbits.UTXISEL0 = 1; // Set to generate TX interrupt when all
U2STAbits.UTXISEL1 = 0; // transmit operations are complete.
...
U2TXInterrupt(void)
{
while(U2STAbits.TRMT==0); // wait for the transmit buffer to be empty
... // process interrupt