Information

PIC24FJ128GA010 FAMILY
DS80471B-page 16  2009-2011 Microchip Technology Inc.
56. Module: I
2
C
The Transmit Buffer Full (TBF) flag (I2CxSTAT<0>)
may not be cleared by hardware if a collision on the
I
2
C bus occurs before the first falling clock edge
during a transmission.
Work around
None.
Affected Silicon Revisions
57. Module: SPI (Master Mode)
In Master mode, the SPIx Interrupt Flag (SPIxIF)
and the SPIRBF bit (SPIxSTAT<0>) may both
become set one-half clock cycle early, instead of
on the clock edge. This occurs only under the
following circumstances:
• Enhanced Buffer mode is disabled
(SPIBEN = 0); and
• the module is configured for serial data output
changes on transition from clock active to clock
Idle state (CKE = 1)
If the application is using the interrupt flag to deter-
mine when data to be transmitted is written to the
transmit buffer, the data currently in the buffer may
be overwritten.
Work around
Before writing to the SPIx buffer, check the SCKx pin
to determine if the last clock edge has passed.
Example 1 (below) demonstrates a method for
doing this. In this example, the RD1 pin functions as
the SPIx clock, SCKx, which is configured as Idle
low.
Affected Silicon Revisions
EXAMPLE 1: CHECKING THE STATE OF SPIxIF AGAINST THE SPIx CLOCK
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
while(IFS0bits.SPI1IF == 0){} //wait for the transmission to complete
while(PORTDbits.RD1 == 1){} //wait for the last clock to finish
SPI1BUF = 0xFF; //write new data to the buffer