Information

2009-2011 Microchip Technology Inc. DS80471B-page 15
PIC24FJ128GA010 FAMILY
51. Module: UART (UERIF Interrupt)
The UART error interrupt may not occur, or occur
at an incorrect time, if multiple errors occur during
a short period of time.
Work around
Read the error flags in the UxSTA register when-
ever a byte is received to verify the error status. In
most cases, these bits will be correct, even if the
UART error interrupt fails to occur. For possible
exceptions, refer to Errata # 52.
Affected Silicon Revisions
52. Module: UART (FIFO Error Flags)
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO. This has only been observed
when both of the following conditions are met:
the UART receive interrupt is set to occur when
the FIFO is full or ¾ full (UxSTA<7:6> = 1x);
and
more than 2 bytes with an error are received.
In these cases, only the first two bytes with a parity
or framing error will have the corresponding bits
indicate correctly. The error bits will not be set after
this.
Work around
None.
Affected Silicon Revisions
53. Module: UART
The UART may not transmit if data is written to
TXxREG before the module is enabled.
Work around
To ensure transmission occurs, always enable the
UART before the buffer is loaded. Use the proce-
dure in Section 16.2 “Transmitting in 8-Bit Data
Mode” or Section 16.3 “Transmitting in 9-Bit
Data Mode of the device data sheet (DS39747).
Affected Silicon Revisions
54. Module: I
2
C (Master Mode)
Under certain circumstances, a module operating
in Master mode may Acknowledge its own com-
mand addressed to a slave device. This happens
when the following occurs:
10-Bit Addressing mode is used (A10M = 1);
and
•the I
2
C master has the same two upper
address bits (I2CADD<9:8>) as the addressed
slave module.
In these cases, the master also Acknowledges the
address command and generates an erroneous
I
2
C
slave interrupt, as well as the
I
2
C
master interrupt.
Work around
Several options are available:
When using 10-Bit Addressing mode, make
certain that the master and slave devices do not
share the same 2 MSbs of their addresses.
If this cannot be avoided:
Clear the A10M bit (I2CxCON<10> = 0) prior to
performing a Master mode transmit.
Read the ADD10 bit (I2CxSTAT<8>) to check
for a full 10-bit match whenever a slave I
2
C
interrupt occurs on the master module.
Affected Silicon Revisions
55. Module: I
2
C (Slave Mode)
Under certain circumstances, a module operating
in Slave mode may not respond correctly to some
of the special addresses reserved by the I
2
C
protocol. This happens when the following occurs:
10-Bit Addressing mode is used (A10M = 1);
and
the A<7:1> bits of the slave address
(I2CADD<7:1>) fall into the range of the
reserved 7-bit address ranges: ‘1111xxx’ or
0000xxx’.
In these cases, the Slave module Acknowledges
the command and triggers an I
2
C slave interrupt; it
does not copy the data into the I2CxRCV register
or set the RBF bit.
Work around
Do not set bits, A<7:1>, of the module’s slave
address equal to 1111xxx’ or ‘0000xxx’.
Affected Silicon Revisions
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX